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Searched refs:RISCV_MMU_VA_WIDTH (Results 1 – 3 of 3) sorted by relevance

/optee_os/core/arch/riscv/include/mm/
H A Dcore_mmu_arch.h45 #define RISCV_MMU_VA_WIDTH U(57) macro
53 #define RISCV_MMU_VA_WIDTH U(48) macro
61 #define RISCV_MMU_VA_WIDTH U(39) macro
69 #define RISCV_MMU_VA_WIDTH U(32) macro
75 #define RISCV_PGLEVELS ((RISCV_MMU_VA_WIDTH - RISCV_PGSHIFT) / \
199 return RISCV_MMU_VA_WIDTH; in core_mmu_get_va_width()
216 vaddr_t mask = GENMASK_64(63, RISCV_MMU_VA_WIDTH); in core_mmu_va_is_valid()
217 uint64_t msb = BIT64(RISCV_MMU_VA_WIDTH - 1); in core_mmu_va_is_valid()
/optee_os/core/include/mm/
H A Dcore_mmu.h482 va &= ~GENMASK_64(63, RISCV_MMU_VA_WIDTH); in core_mmu_va2idx()
/optee_os/core/arch/riscv/mm/
H A Dcore_mmu_arch.c272 vaddr_t va_width_msb = BIT64(RISCV_MMU_VA_WIDTH - 1); in core_mmu_pgt_get_va_base()
273 vaddr_t va_extended_mask = GENMASK_64(63, RISCV_MMU_VA_WIDTH); in core_mmu_pgt_get_va_base()