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Searched refs:JRX_JRCFGR_LS (Results 1 – 2 of 2) sorted by relevance

/optee_os/core/drivers/crypto/caam/hal/common/
H A Dhal_jr.c25 BACKUP_REG(JRX_JRCFGR_LS, 1, 0, 0),
41 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_reset()
112 io_caam_write32(baseaddr + JRX_JRCFGR_LS, value); in caam_hal_jr_config()
142 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_disable_itr()
148 io_mask32(baseaddr + JRX_JRCFGR_LS, ~JRX_JRCFGR_LS_IMSK, in caam_hal_jr_enable_itr()
177 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_halt()
207 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_flush()
/optee_os/core/drivers/crypto/caam/hal/common/registers/
H A Djr_regs.h49 #define JRX_JRCFGR_LS 0x0054 macro