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Searched refs:vlevel (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c2652 int vlevel, argument
2715 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2716 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2717 v->ModeSupport[vlevel][0])
2720 if (vlevel > context->bw_ctx.dml.soc.num_states)
2721 vlevel = vlevel_split;
2739 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2741 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
2755 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
2760 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
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H A Ddcn20_resource.h124 int vlevel,
160 int vlevel);
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c1026 int vlevel, in calculate_wm_set_for_vlevel() argument
1035 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1037 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
1038 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1039 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1095 int vlevel, vlevel_max; in dcn21_calculate_wm() local
1148 vlevel = 0; in dcn21_calculate_wm()
1150 vlevel = vlevel_max; in dcn21_calculate_wm()
1151 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn21_calculate_wm()
1155 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max); in dcn21_calculate_wm()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c1956 int pipe_cnt, i, pipe_idx, vlevel; in dcn30_internal_validate_bw() local
1980 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1982 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1983 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1985 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1986 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { in dcn30_internal_validate_bw()
1997 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1998 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
2001 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
2010 vlevel = 0; in dcn30_internal_validate_bw()
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H A Ddcn30_resource.h62 int vlevel);
/OK3568_Linux_fs/kernel/arch/arm64/kvm/
H A Darch_timer.c635 bool vlevel, plevel; in kvm_timer_should_notify_user() local
640 vlevel = sregs->device_irq_level & KVM_ARM_DEV_EL1_VTIMER; in kvm_timer_should_notify_user()
643 return kvm_timer_should_fire(vtimer) != vlevel || in kvm_timer_should_notify_user()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h108 int vlevel);