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Searched refs:tiles_enabled_flag (Results 1 – 11 of 11) sorted by relevance

/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_rkv.c376 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_v345_output_pps_packet()
388 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_columns_minus1 + 1 : 0, … in hal_h265d_v345_output_pps_packet()
389 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_rows_minus1 + 1 : 0 , 5 … in hal_h265d_v345_output_pps_packet()
400 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_v345_output_pps_packet()
587 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_output_pps_packet()
614 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_output_pps_packet()
891 hw_regs->sw_interrupt.sw_wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_rkv_gen_regs()
H A Dhal_h265d_vdpu34x.c326 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_v345_output_pps_packet()
338 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_columns_minus1 + 1 : 0, … in hal_h265d_v345_output_pps_packet()
339 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_rows_minus1 + 1 : 0 , 5 … in hal_h265d_v345_output_pps_packet()
350 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_v345_output_pps_packet()
554 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1); in hal_h265d_output_pps_packet()
580 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_output_pps_packet()
1029 hw_regs->common.reg012.wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_vdpu34x_gen_regs()
H A Dhal_h265d_vdpu382.c330 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_v382_output_pps_packet()
342 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_columns_minus1 + 1 : 0, … in hal_h265d_v382_output_pps_packet()
343 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_rows_minus1 + 1 : 0 , 5 … in hal_h265d_v382_output_pps_packet()
354 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_v382_output_pps_packet()
/OK3568_Linux_fs/external/mpp/mpp/codec/dec/h265/
H A Dh265d_ps.c925 if (openhevc_pps->tiles_enabled_flag != pps->tiles_enabled_flag) { in compare_pps()
1990 READ_ONEBIT(gb, &pps->tiles_enabled_flag); in mpp_hevc_decode_nal_pps()
1999 RK_S32 max_supt_height = pps->tiles_enabled_flag ? PIXH_1080P : PIXW_1080P; in mpp_hevc_decode_nal_pps()
2003 max_supt_height = pps->tiles_enabled_flag ? PIXH_8Kx4K : PIXW_8Kx4K; in mpp_hevc_decode_nal_pps()
2006 max_supt_height = pps->tiles_enabled_flag ? PIXH_4Kx2K : PIXW_4Kx2K; in mpp_hevc_decode_nal_pps()
2009 … if (sps->width > max_supt_width || (sps->height > max_supt_height && pps->tiles_enabled_flag) in mpp_hevc_decode_nal_pps()
2024 if (pps->tiles_enabled_flag) { in mpp_hevc_decode_nal_pps()
H A Dh265d_parser2_syntax.c130 … (pps->tiles_enabled_flag << 7) | in fill_picture_parameters()
149 if (pps->tiles_enabled_flag) { in fill_picture_parameters()
H A Dh265d_parser.h317 RK_U8 tiles_enabled_flag; member
H A Dh265d_parser.c1043 if (s->pps->tiles_enabled_flag || s->pps->entropy_coding_sync_enabled_flag) { in hls_slice_header()
/OK3568_Linux_fs/external/mpp/mpp/common/
H A Dh265d_syntax.h137 UINT32 tiles_enabled_flag : 1; member
H A Dh265e_syntax_new.h95 RK_U32 tiles_enabled_flag : 1; member
/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu580.c220 if (!syn->pp.tiles_enabled_flag) { in vepu580_h265_set_me_ram()
2331 if (syn->pp.tiles_enabled_flag) { in vepu580_h265_set_hw_address()
2385 RK_S32 tiles_enabled_flag) in vepu580_h265e_save_pass1_patch() argument
2406 if (tiles_enabled_flag) in vepu580_h265e_save_pass1_patch()
2646 setup_vepu580_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag); in hal_h265e_v580_gen_regs()
2649 vepu580_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag); in hal_h265e_v580_gen_regs()
2662 if (syn->pp.tiles_enabled_flag) { in hal_h265e_v580_set_uniform_tile()
2690 regs->reg0252_tile_cfg.tile_en = syn->pp.tiles_enabled_flag; in hal_h265e_v580_set_uniform_tile()
2770 vepu580_h265e_save_pass1_patch(hw_regs, ctx, syn->pp.tiles_enabled_flag); in hal_h265e_v580_start()
H A Dhal_h265e_vepu541.c1363 if (syn->pp.tiles_enabled_flag == 0) { in vepu540_h265_set_me_ram()
1460 if (syn->pp.tiles_enabled_flag) { in vepu54x_h265_set_hw_address()
1698 if (syn->pp.tiles_enabled_flag) { in hal_h265e_v540_set_uniform_tile()
1709 regs->tile_cfg.tile_en = syn->pp.tiles_enabled_flag; in hal_h265e_v540_set_uniform_tile()