Searched refs:tile_rows (Results 1 – 11 of 11) sorted by relevance
109 ctx->params.tile_rows = 480 / 4; in iep2_init()174 ctx->params.tile_rows = 480 / 4; in iep2_init()259 r.h = ctx->params.tile_rows; in iep2_done()308 ctx->params.tile_rows = (param->com.height + 3) / 4; in iep2_set_param()361 ctx->params.tile_rows <= 0 || ctx->params.tile_rows > IEP2_TILE_H_MAX) { in iep2_param_check()363 ctx->params.tile_cols, ctx->params.tile_rows); in iep2_param_check()
71 int rows = ctx->params.tile_rows; in iep2_update_gmv()
52 uint32_t tile_rows; member
1049 current->tile_rows = (sb_rows + tile_height_sb - 1) / tile_height_sb; in mpp_av1_tile_info()1055 for (i = 0; i < current->tile_rows - 1; i++) in mpp_av1_tile_info()1058 sb_rows - (current->tile_rows - 1) * tile_height_sb - 1); in mpp_av1_tile_info()1091 current->tile_rows = i; in mpp_av1_tile_info()1105 ctx->tile_rows = current->tile_rows; in mpp_av1_tile_info()2110 ctx->tile_rows, ctx->tile_cols); in mpp_av1_uncompressed_header()2210 num_tiles = ctx->tile_cols * ctx->tile_rows; in mpp_av1_tile_group_obu()2221 mpp_av1_tile_log2(1, ctx->tile_rows); in mpp_av1_tile_group_obu()
115 RK_S32 tile_rows; member
219 RK_U16 tile_rows; member
51 pp->tiles.rows = frame_header->tile_rows; in av1d_fill_picparams()
183 RK_U32 tile_cols, tile_rows; member
1038 s->tiling.tile_rows = 1 << s->tiling.log2_tile_rows; in decode_parser_header()
101 u32 tile_rows; member362 height = cfg->tile_rows * TILE_HEIGHT; in iep2_config()
2475 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local2487 tile_rows = *y / tile_height; in intel_compute_aligned_offset()2493 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()