| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn.h | 70 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
76 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
80 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
88 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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| H A D | vcn_v1_0.c | 641 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) in vcn_v1_0_clock_gating_dpg_mode() argument
652 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
654 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
683 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
686 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
689 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
692 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
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| H A D | vcn_v2_5.c | 662 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v2_5_clock_gating_dpg_mode() argument
694 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
698 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
702 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
706 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
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| H A D | vcn_v2_0.c | 594 uint8_t sram_sel, uint8_t indirect) in vcn_v2_0_clock_gating_dpg_mode() argument
626 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
630 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
634 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
638 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
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| H A D | vcn_v3_0.c | 781 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v3_0_clock_gating_dpg_mode() argument
813 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
817 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
821 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
825 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
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