Searched refs:slice_alpha_c0_offset_div2 (Results 1 – 13 of 13) sorted by relevance
70 slice->slice_alpha_c0_offset_div2 = h264->deblock_offset_alpha; in h264e_slice_update()503 ret |= mpp_read_se(&bit, &slice->slice_alpha_c0_offset_div2); in h264e_slice_read()505 bit.used_bits, slice->slice_alpha_c0_offset_div2); in h264e_slice_read()711 mpp_writer_put_se(s, slice->slice_alpha_c0_offset_div2); in h264e_slice_write_header()713 mpp_writer_bits(s), slice->slice_alpha_c0_offset_div2); in h264e_slice_write_header()
113 RK_S32 slice_alpha_c0_offset_div2; member
168 __s8 slice_alpha_c0_offset_div2; member
144 RK_S8 slice_alpha_c0_offset_div2;
480 …RK_S32 slice_alpha_c0_offset_div2; /* RW; Range:[-6,+6]; see the H.264 protocol for t… member
441 reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; in cedrus_set_params()
296 s16 slice_alpha_c0_offset_div2; member
439 | VEPU_REG_SLICE_FILTER_ALPHA(slice->slice_alpha_c0_offset_div2) in hal_h264e_vepu1_gen_regs_v2()
486 | VEPU_REG_SLICE_FILTER_ALPHA(slice->slice_alpha_c0_offset_div2) in hal_h264e_vepu2_gen_regs_v2()
586 regs->reg108.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu541_codec()
570 regs->reg_base.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu540c_codec()
915 regs->reg_base.synt_sli2.sli_alph_ofst = slice->slice_alpha_c0_offset_div2; in setup_vepu580_codec()
1106 This value corresponds to the slice_alpha_c0_offset_div2 slice header1915 - ``slice_alpha_c0_offset_div2``