1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2017 Realtek Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in the 16 * file called LICENSE. 17 * 18 * Contact Information: 19 * wlanfae <wlanfae@realtek.com> 20 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 21 * Hsinchu 300, Taiwan. 22 * 23 * Larry Finger <Larry.Finger@lwfinger.net> 24 * 25 *****************************************************************************/ 26 27 #ifndef __HALDMOUTSRC_H__ 28 #define __HALDMOUTSRC_H__ 29 30 /*@============================================================*/ 31 /*@include files*/ 32 /*@============================================================*/ 33 /*PHYDM header*/ 34 #include "phydm_pre_define.h" 35 #include "phydm_features.h" 36 #include "phydm_dig.h" 37 #ifdef CONFIG_PATH_DIVERSITY 38 #include "phydm_pathdiv.h" 39 #endif 40 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 41 #include "phydm_antdiv.h" 42 #endif 43 44 #include "phydm_soml.h" 45 46 #ifdef CONFIG_SMART_ANTENNA 47 #include "phydm_smt_ant.h" 48 #endif 49 #ifdef CONFIG_ANT_DETECTION 50 #include "phydm_antdect.h" 51 #endif 52 #include "phydm_rainfo.h" 53 #ifdef CONFIG_DYNAMIC_TX_TWR 54 #include "phydm_dynamictxpower.h" 55 #endif 56 #include "phydm_cfotracking.h" 57 #include "phydm_adaptivity.h" 58 #include "phydm_dfs.h" 59 #include "phydm_ccx.h" 60 #include "txbf/phydm_hal_txbf_api.h" 61 #if (PHYDM_LA_MODE_SUPPORT) 62 #include "phydm_adc_sampling.h" 63 #endif 64 #ifdef CONFIG_PSD_TOOL 65 #include "phydm_psd.h" 66 #endif 67 #ifdef PHYDM_PRIMARY_CCA 68 #include "phydm_primary_cca.h" 69 #endif 70 #include "phydm_cck_pd.h" 71 #include "phydm_rssi_monitor.h" 72 #ifdef PHYDM_AUTO_DEGBUG 73 #include "phydm_auto_dbg.h" 74 #endif 75 #include "phydm_math_lib.h" 76 #include "phydm_noisemonitor.h" 77 #include "phydm_api.h" 78 #ifdef PHYDM_POWER_TRAINING_SUPPORT 79 #include "phydm_pow_train.h" 80 #endif 81 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 82 #include "phydm_lna_sat.h" 83 #endif 84 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 85 #include "phydm_pmac_tx_setting.h" 86 #endif 87 #ifdef PHYDM_MP_SUPPORT 88 #include "phydm_mp.h" 89 #endif 90 91 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 92 #include "phydm_cck_rx_pathdiv.h" 93 #endif 94 95 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 96 #include "phydm_beamforming.h" 97 #endif 98 99 #ifdef CONFIG_DIRECTIONAL_BF 100 #include "phydm_direct_bf.h" 101 #endif 102 103 #include "phydm_regtable.h" 104 105 /*@HALRF header*/ 106 #include "halrf/halrf_iqk.h" 107 #include "halrf/halrf_dpk.h" 108 #include "halrf/halrf.h" 109 #include "halrf/halrf_powertracking.h" 110 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 111 #include "halrf/halphyrf_ap.h" 112 #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) 113 #include "halrf/halphyrf_ce.h" 114 #elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 115 #include "halrf/halphyrf_win.h" 116 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 117 #include "halrf/halphyrf_iot.h" 118 #endif 119 120 extern const u16 phy_rate_table[84]; 121 122 /*@============================================================*/ 123 /*@Definition */ 124 /*@============================================================*/ 125 126 /* Traffic load decision */ 127 #define TRAFFIC_NO_TP 0 128 #define TRAFFIC_ULTRA_LOW 1 129 #define TRAFFIC_LOW 2 130 #define TRAFFIC_MID 3 131 #define TRAFFIC_HIGH 4 132 133 #define NONE 0 134 135 #if defined(DM_ODM_CE_MAC80211) 136 #define MAX_2(x, y) \ 137 __max2(typeof(x), typeof(y), \ 138 x, y) 139 #define __max2(t1, t2, x, y) ({ \ 140 t1 m80211_max1 = (x); \ 141 t2 m80211_max2 = (y); \ 142 m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) 143 144 #define MIN_2(x, y) \ 145 __min2(typeof(x), typeof(y), \ 146 x, y) 147 #define __min2(t1, t2, x, y) ({ \ 148 t1 m80211_min1 = (x); \ 149 t2 m80211_min2 = (y); \ 150 m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) 151 152 #define DIFF_2(x, y) \ 153 __diff2(typeof(x), typeof(y), \ 154 x, y) 155 #define __diff2(t1, t2, x, y) ({ \ 156 t1 __d1 = (x); \ 157 t2 __d2 = (y); \ 158 (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) 159 #else 160 #define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) 161 #define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) 162 #define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) 163 #endif 164 165 #define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) 166 #define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) 167 168 #if defined(DM_ODM_CE_MAC80211) 169 #define BYTE_DUPLICATE_2_DWORD(B0) ({ \ 170 u32 __b_dup = (B0);\ 171 (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ 172 }) 173 #else 174 #define BYTE_DUPLICATE_2_DWORD(B0) \ 175 (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) 176 #endif 177 #define BYTE_2_DWORD(B3, B2, B1, B0) \ 178 (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) 179 #define BIT_2_BYTE(B3, B2, B1, B0) \ 180 (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) 181 182 /*@For cmn sta info*/ 183 #if defined(DM_ODM_CE_MAC80211) 184 #define is_sta_active(sta) ({ \ 185 struct cmn_sta_info *__sta = (sta); \ 186 ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ 187 }) 188 189 #define IS_FUNC_EN(name) ({ \ 190 u8 *__is_func_name = (name); \ 191 (__is_func_name) && (*__is_func_name); \ 192 }) 193 #else 194 #define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) 195 196 #define IS_FUNC_EN(name) ((name) && (*name)) 197 #endif 198 199 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 200 #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ 201 #else 202 #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ 203 #endif 204 205 #define PHY_HIST_SIZE 12 206 #define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1) 207 208 /*@============================================================*/ 209 /*structure and define*/ 210 /*@============================================================*/ 211 212 #define dm_type_by_fw 0 213 #define dm_type_by_driver 1 214 215 #ifdef BB_RAM_SUPPORT 216 217 struct phydm_bb_ram_per_sta { 218 /* @Reg0x1E84 for RAM I/O*/ 219 boolean hw_igi_en; 220 boolean tx_pwr_offset0_en; 221 boolean tx_pwr_offset1_en; 222 /* @ macid from 0 to 63, above 63 => mapping to 63*/ 223 u8 macid_addr; 224 /* @hw_igi value for paths after packet Tx in a period of time*/ 225 u8 hw_igi; 226 /* @tx_pwr_offset0 offset for Tx power index*/ 227 s8 tx_pwr_offset0; 228 s8 tx_pwr_offset1; 229 230 }; 231 232 struct phydm_bb_ram_ctrl { 233 /*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/ 234 struct phydm_bb_ram_per_sta pram_sta_ctrl[64]; 235 /*------------ For table2 do not set power offset by macid --------*/ 236 /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ 237 boolean tx_pwr_ofst_reg0_en; 238 u8 tx_pwr_ofst_reg0; 239 /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ 240 boolean tx_pwr_ofst_reg1_en; 241 u8 tx_pwr_ofst_reg1; 242 boolean hwigi_watchdog_en; 243 }; 244 245 #endif 246 247 struct phydm_phystatus_statistic { 248 /*@[CCK]*/ 249 u32 rssi_cck_sum; 250 u32 rssi_cck_cnt; 251 u32 rssi_beacon_sum[RF_PATH_MEM_SIZE]; 252 u32 rssi_beacon_cnt; 253 #ifdef PHYSTS_3RD_TYPE_SUPPORT 254 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 255 u32 rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1]; 256 #endif 257 #endif 258 /*@[OFDM]*/ 259 u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE]; 260 u32 rssi_ofdm_cnt; 261 u32 evm_ofdm_sum; 262 u32 snr_ofdm_sum[RF_PATH_MEM_SIZE]; 263 u16 evm_ofdm_hist[PHY_HIST_SIZE]; 264 u16 snr_ofdm_hist[PHY_HIST_SIZE]; 265 /*@[1SS]*/ 266 u32 rssi_1ss_cnt; 267 u32 rssi_1ss_sum[RF_PATH_MEM_SIZE]; 268 u32 evm_1ss_sum; 269 u32 snr_1ss_sum[RF_PATH_MEM_SIZE]; 270 u16 evm_1ss_hist[PHY_HIST_SIZE]; 271 u16 snr_1ss_hist[PHY_HIST_SIZE]; 272 /*@[2SS]*/ 273 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 274 u32 rssi_2ss_cnt; 275 u32 rssi_2ss_sum[RF_PATH_MEM_SIZE]; 276 u32 evm_2ss_sum[2]; 277 u32 snr_2ss_sum[RF_PATH_MEM_SIZE]; 278 u16 evm_2ss_hist[2][PHY_HIST_SIZE]; 279 u16 snr_2ss_hist[2][PHY_HIST_SIZE]; 280 #endif 281 /*@[3SS]*/ 282 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 283 u32 rssi_3ss_cnt; 284 u32 rssi_3ss_sum[RF_PATH_MEM_SIZE]; 285 u32 evm_3ss_sum[3]; 286 u32 snr_3ss_sum[RF_PATH_MEM_SIZE]; 287 u16 evm_3ss_hist[3][PHY_HIST_SIZE]; 288 u16 snr_3ss_hist[3][PHY_HIST_SIZE]; 289 #endif 290 /*@[4SS]*/ 291 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 292 u32 rssi_4ss_cnt; 293 u32 rssi_4ss_sum[RF_PATH_MEM_SIZE]; 294 u32 evm_4ss_sum[4]; 295 u32 snr_4ss_sum[RF_PATH_MEM_SIZE]; 296 u16 evm_4ss_hist[4][PHY_HIST_SIZE]; 297 u16 snr_4ss_hist[4][PHY_HIST_SIZE]; 298 #endif 299 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 300 u16 p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/ 301 u16 cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/ 302 u16 cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE]; 303 #endif 304 }; 305 306 struct phydm_phystatus_avg { 307 /*@[CCK]*/ 308 u8 rssi_cck_avg; 309 u8 rssi_beacon_avg[RF_PATH_MEM_SIZE]; 310 #ifdef PHYSTS_3RD_TYPE_SUPPORT 311 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 312 u8 rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1]; 313 #endif 314 #endif 315 /*@[OFDM]*/ 316 u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE]; 317 u8 evm_ofdm_avg; 318 u8 snr_ofdm_avg[RF_PATH_MEM_SIZE]; 319 /*@[1SS]*/ 320 u8 rssi_1ss_avg[RF_PATH_MEM_SIZE]; 321 u8 evm_1ss_avg; 322 u8 snr_1ss_avg[RF_PATH_MEM_SIZE]; 323 /*@[2SS]*/ 324 #if (defined(PHYDM_COMPILE_ABOVE_2SS)) 325 u8 rssi_2ss_avg[RF_PATH_MEM_SIZE]; 326 u8 evm_2ss_avg[2]; 327 u8 snr_2ss_avg[RF_PATH_MEM_SIZE]; 328 #endif 329 /*@[3SS]*/ 330 #if (defined(PHYDM_COMPILE_ABOVE_3SS)) 331 u8 rssi_3ss_avg[RF_PATH_MEM_SIZE]; 332 u8 evm_3ss_avg[3]; 333 u8 snr_3ss_avg[RF_PATH_MEM_SIZE]; 334 #endif 335 /*@[4SS]*/ 336 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 337 u8 rssi_4ss_avg[RF_PATH_MEM_SIZE]; 338 u8 evm_4ss_avg[4]; 339 u8 snr_4ss_avg[RF_PATH_MEM_SIZE]; 340 #endif 341 }; 342 343 struct odm_phy_dbg_info { 344 /*@ODM Write,debug info*/ 345 u32 num_qry_phy_status_cck; 346 u32 num_qry_phy_status_ofdm; 347 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) 348 u32 num_qry_mu_pkt; 349 u32 num_qry_bf_pkt; 350 u16 num_mu_vht_pkt[VHT_RATE_NUM]; 351 boolean is_ldpc_pkt; 352 boolean is_stbc_pkt; 353 u8 num_of_ppdu[4]; 354 u8 gid_num[4]; 355 #endif 356 u32 condi_num; /*@condition number U(18,4)*/ 357 u8 condi_num_cdf[CN_CNT_MAX]; 358 u8 num_qry_beacon_pkt; 359 u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ 360 u8 beacon_phy_rate; 361 u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ 362 u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ 363 u16 show_phy_sts_cnt; 364 u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; 365 u16 num_qry_ht_pkt[HT_RATE_NUM]; 366 u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ 367 boolean ht_pkt_not_zero; 368 boolean low_bw_20_occur; 369 #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT) 370 u16 num_qry_vht_pkt[VHT_RATE_NUM]; 371 u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ 372 boolean vht_pkt_not_zero; 373 boolean low_bw_40_occur; 374 #endif 375 u16 snr_hist_th[PHY_HIST_TH_SIZE]; 376 u16 evm_hist_th[PHY_HIST_TH_SIZE]; 377 #ifdef PHYSTS_3RD_TYPE_SUPPORT 378 u16 cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/ 379 u8 condition_num_seg0; 380 u8 eigen_val[4]; 381 s16 cfo_tail[4]; /*per-path's cfo_tail */ 382 #endif 383 struct phydm_phystatus_statistic physts_statistic_info; 384 struct phydm_phystatus_avg phystatus_statistic_avg; 385 }; 386 387 enum odm_cmninfo { 388 /*@Fixed value*/ 389 /*@-----------HOOK BEFORE REG INIT-----------*/ 390 ODM_CMNINFO_PLATFORM = 0, 391 ODM_CMNINFO_ABILITY, 392 ODM_CMNINFO_INTERFACE, 393 ODM_CMNINFO_MP_TEST_CHIP, 394 ODM_CMNINFO_IC_TYPE, 395 ODM_CMNINFO_CUT_VER, 396 ODM_CMNINFO_FAB_VER, 397 ODM_CMNINFO_FW_VER, 398 ODM_CMNINFO_FW_SUB_VER, 399 ODM_CMNINFO_RF_TYPE, 400 ODM_CMNINFO_RFE_TYPE, 401 ODM_CMNINFO_DPK_EN, 402 ODM_CMNINFO_BOARD_TYPE, 403 ODM_CMNINFO_PACKAGE_TYPE, 404 ODM_CMNINFO_EXT_LNA, 405 ODM_CMNINFO_5G_EXT_LNA, 406 ODM_CMNINFO_EXT_PA, 407 ODM_CMNINFO_5G_EXT_PA, 408 ODM_CMNINFO_GPA, 409 ODM_CMNINFO_APA, 410 ODM_CMNINFO_GLNA, 411 ODM_CMNINFO_ALNA, 412 ODM_CMNINFO_TDMA, 413 ODM_CMNINFO_EXT_TRSW, 414 ODM_CMNINFO_EXT_LNA_GAIN, 415 ODM_CMNINFO_PATCH_ID, 416 ODM_CMNINFO_BINHCT_TEST, 417 ODM_CMNINFO_BWIFI_TEST, 418 ODM_CMNINFO_SMART_CONCURRENT, 419 ODM_CMNINFO_CONFIG_BB_RF, 420 ODM_CMNINFO_IQKPAOFF, 421 ODM_CMNINFO_HUBUSBMODE, 422 ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, 423 ODM_CMNINFO_TX_TP, 424 ODM_CMNINFO_RX_TP, 425 ODM_CMNINFO_SOUNDING_SEQ, 426 ODM_CMNINFO_REGRFKFREEENABLE, 427 ODM_CMNINFO_RFKFREEENABLE, 428 ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, 429 ODM_CMNINFO_VALID_PATH_SET, 430 ODM_CMNINFO_EFUSE0X3D8, 431 ODM_CMNINFO_EFUSE0X3D7, 432 ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, 433 ODM_CMNINFO_X_CAP_SETTING, 434 ODM_CMNINFO_ADVANCE_OTA, 435 ODM_CMNINFO_HP_HWID, 436 ODM_CMNINFO_TSSI_ENABLE, 437 ODM_CMNINFO_DIS_DPD, 438 ODM_CMNINFO_POWER_VOLTAGE, 439 ODM_CMNINFO_ANTDIV_GPIO, 440 ODM_CMNINFO_EN_AUTO_BW_TH, 441 ODM_CMNINFO_PEAK_DETECT_MODE, 442 /*@-----------HOOK BEFORE REG INIT-----------*/ 443 444 /*@Dynamic value:*/ 445 446 /*@--------- POINTER REFERENCE-----------*/ 447 ODM_CMNINFO_TX_UNI, 448 ODM_CMNINFO_RX_UNI, 449 ODM_CMNINFO_BAND, 450 ODM_CMNINFO_SEC_CHNL_OFFSET, 451 ODM_CMNINFO_SEC_MODE, 452 ODM_CMNINFO_BW, 453 ODM_CMNINFO_CHNL, 454 ODM_CMNINFO_FORCED_RATE, 455 ODM_CMNINFO_ANT_DIV, 456 ODM_CMNINFO_PATH_DIV, 457 ODM_CMNINFO_ADAPTIVE_SOML, 458 ODM_CMNINFO_ADAPTIVITY, 459 ODM_CMNINFO_SCAN, 460 ODM_CMNINFO_POWER_SAVING, 461 ODM_CMNINFO_ONE_PATH_CCA, 462 ODM_CMNINFO_DRV_STOP, 463 ODM_CMNINFO_PNP_IN, 464 ODM_CMNINFO_INIT_ON, 465 ODM_CMNINFO_ANT_TEST, 466 ODM_CMNINFO_NET_CLOSED, 467 ODM_CMNINFO_P2P_LINK, 468 ODM_CMNINFO_FCS_MODE, 469 ODM_CMNINFO_IS1ANTENNA, 470 ODM_CMNINFO_RFDEFAULTPATH, 471 ODM_CMNINFO_DFS_MASTER_ENABLE, 472 ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, 473 ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, 474 ODM_CMNINFO_SOFT_AP_MODE, 475 ODM_CMNINFO_MP_MODE, 476 ODM_CMNINFO_INTERRUPT_MASK, 477 ODM_CMNINFO_BB_OPERATION_MODE, 478 ODM_CMNINFO_BF_ANTDIV_DECISION, 479 ODM_CMNINFO_MANUAL_SUPPORTABILITY, 480 ODM_CMNINFO_EN_DYM_BW_INDICATION, 481 /*@--------- POINTER REFERENCE-----------*/ 482 483 /*@------------CALL BY VALUE-------------*/ 484 ODM_CMNINFO_WIFI_DIRECT, 485 ODM_CMNINFO_WIFI_DISPLAY, 486 ODM_CMNINFO_LINK_IN_PROGRESS, 487 ODM_CMNINFO_LINK, 488 ODM_CMNINFO_CMW500LINK, 489 ODM_CMNINFO_STATION_STATE, 490 ODM_CMNINFO_RSSI_MIN, 491 ODM_CMNINFO_RSSI_MIN_BY_PATH, 492 ODM_CMNINFO_DBG_COMP, 493 ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ 494 ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ 495 ODM_CMNINFO_RF_ANTENNA_TYPE, 496 ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, 497 ODM_CMNINFO_BE_FIX_TX_ANT, 498 ODM_CMNINFO_BT_ENABLED, 499 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 500 ODM_CMNINFO_BT_HS_RSSI, 501 ODM_CMNINFO_BT_OPERATION, 502 ODM_CMNINFO_BT_LIMITED_DIG, 503 ODM_CMNINFO_AP_TOTAL_NUM, 504 ODM_CMNINFO_POWER_TRAINING, 505 ODM_CMNINFO_DFS_REGION_DOMAIN, 506 ODM_CMNINFO_BT_CONTINUOUS_TURN, 507 ODM_CMNINFO_IS_DOWNLOAD_FW, 508 ODM_CMNINFO_PHYDM_PATCH_ID, 509 ODM_CMNINFO_RRSR_VAL, 510 ODM_CMNINFO_LINKED_BF_SUPPORT, 511 ODM_CMNINFO_FLATNESS_TYPE, 512 /*@------------CALL BY VALUE-------------*/ 513 514 /*@Dynamic ptr array hook itms.*/ 515 ODM_CMNINFO_STA_STATUS, 516 ODM_CMNINFO_MAX, 517 518 }; 519 520 enum phydm_rfe_bb_source_sel { 521 PAPE_2G = 0, 522 PAPE_5G = 1, 523 LNA0N_2G = 2, 524 LNAON_5G = 3, 525 TRSW = 4, 526 TRSW_B = 5, 527 GNT_BT = 6, 528 ZERO = 7, 529 ANTSEL_0 = 8, 530 ANTSEL_1 = 9, 531 ANTSEL_2 = 0xa, 532 ANTSEL_3 = 0xb, 533 ANTSEL_4 = 0xc, 534 ANTSEL_5 = 0xd, 535 ANTSEL_6 = 0xe, 536 ANTSEL_7 = 0xf 537 }; 538 539 enum phydm_info_query { 540 PHYDM_INFO_FA_OFDM, 541 PHYDM_INFO_FA_CCK, 542 PHYDM_INFO_FA_TOTAL, 543 PHYDM_INFO_CCA_OFDM, 544 PHYDM_INFO_CCA_CCK, 545 PHYDM_INFO_CCA_ALL, 546 PHYDM_INFO_CRC32_OK_VHT, 547 PHYDM_INFO_CRC32_OK_HT, 548 PHYDM_INFO_CRC32_OK_LEGACY, 549 PHYDM_INFO_CRC32_OK_CCK, 550 PHYDM_INFO_CRC32_ERROR_VHT, 551 PHYDM_INFO_CRC32_ERROR_HT, 552 PHYDM_INFO_CRC32_ERROR_LEGACY, 553 PHYDM_INFO_CRC32_ERROR_CCK, 554 PHYDM_INFO_EDCCA_FLAG, 555 PHYDM_INFO_OFDM_ENABLE, 556 PHYDM_INFO_CCK_ENABLE, 557 PHYDM_INFO_CRC32_OK_HT_AGG, 558 PHYDM_INFO_CRC32_ERROR_HT_AGG, 559 PHYDM_INFO_DBG_PORT_0, 560 PHYDM_INFO_CURR_IGI, 561 PHYDM_INFO_RSSI_MIN, 562 PHYDM_INFO_RSSI_MAX, 563 PHYDM_INFO_CLM_RATIO, 564 PHYDM_INFO_NHM_RATIO, 565 PHYDM_INFO_NHM_NOISE_PWR, 566 }; 567 568 enum phydm_api { 569 PHYDM_API_NBI = 1, 570 PHYDM_API_CSI_MASK = 2, 571 }; 572 573 enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ 574 575 F00_DIG = 0, 576 F01_RA_MASK = 1, 577 F02_DYN_TXPWR = 2, 578 F03_FA_CNT = 3, 579 F04_RSSI_MNTR = 4, 580 F05_CCK_PD = 5, 581 F06_ANT_DIV = 6, 582 F07_SMT_ANT = 7, 583 F08_PWR_TRAIN = 8, 584 F09_RA = 9, 585 F10_PATH_DIV = 10, 586 F11_DFS = 11, 587 F12_DYN_ARFR = 12, 588 F13_ADPTVTY = 13, 589 F14_CFO_TRK = 14, 590 F15_ENV_MNTR = 15, 591 F16_PRI_CCA = 16, 592 F17_ADPTV_SOML = 17, 593 F18_LNA_SAT_CHK = 18, 594 }; 595 596 /*@=[PHYDM supportability]==========================================*/ 597 enum odm_ability { 598 ODM_BB_DIG = BIT(F00_DIG), 599 ODM_BB_RA_MASK = BIT(F01_RA_MASK), 600 ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), 601 ODM_BB_FA_CNT = BIT(F03_FA_CNT), 602 ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), 603 ODM_BB_CCK_PD = BIT(F05_CCK_PD), 604 ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), 605 ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), 606 ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), 607 ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), 608 ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), 609 ODM_BB_DFS = BIT(F11_DFS), 610 ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), 611 ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), 612 ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), 613 ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), 614 ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), 615 ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), 616 ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 617 }; 618 619 /*@=[PHYDM Debug Component]=====================================*/ 620 enum phydm_dbg_comp { 621 /*@BB Driver Functions*/ 622 DBG_DIG = BIT(F00_DIG), 623 DBG_RA_MASK = BIT(F01_RA_MASK), 624 DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), 625 DBG_FA_CNT = BIT(F03_FA_CNT), 626 DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), 627 DBG_CCKPD = BIT(F05_CCK_PD), 628 DBG_ANT_DIV = BIT(F06_ANT_DIV), 629 DBG_SMT_ANT = BIT(F07_SMT_ANT), 630 DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), 631 DBG_RA = BIT(F09_RA), 632 DBG_PATH_DIV = BIT(F10_PATH_DIV), 633 DBG_DFS = BIT(F11_DFS), 634 DBG_DYN_ARFR = BIT(F12_DYN_ARFR), 635 DBG_ADPTVTY = BIT(F13_ADPTVTY), 636 DBG_CFO_TRK = BIT(F14_CFO_TRK), 637 DBG_ENV_MNTR = BIT(F15_ENV_MNTR), 638 DBG_PRI_CCA = BIT(F16_PRI_CCA), 639 DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), 640 DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), 641 /*Neet to re-arrange*/ 642 DBG_PHY_STATUS = BIT(20), 643 DBG_TMP = BIT(21), 644 DBG_FW_TRACE = BIT(22), 645 DBG_TXBF = BIT(23), 646 DBG_COMMON_FLOW = BIT(24), 647 DBG_COMP_MCC = BIT(25), 648 DBG_FW_DM = BIT(26), 649 DBG_DM_SUMMARY = BIT(27), 650 ODM_PHY_CONFIG = BIT(28), 651 ODM_COMP_INIT = BIT(29), 652 DBG_CMN = BIT(30),/*@common*/ 653 ODM_COMP_API = BIT(31) 654 }; 655 656 /*@=========================================================*/ 657 658 /*@ODM_CMNINFO_ONE_PATH_CCA*/ 659 enum odm_cca_path { 660 ODM_CCA_2R = 0, 661 ODM_CCA_1R_A = 1, 662 ODM_CCA_1R_B = 2, 663 }; 664 665 enum phy_reg_pg_type { 666 PHY_REG_PG_RELATIVE_VALUE = 0, 667 PHY_REG_PG_EXACT_VALUE = 1 668 }; 669 670 enum phydm_offload_ability { 671 PHYDM_PHY_PARAM_OFFLOAD = BIT(0), 672 PHYDM_RF_IQK_OFFLOAD = BIT(1), 673 PHYDM_RF_DPK_OFFLOAD = BIT(2), 674 }; 675 676 enum phydm_init_result { 677 PHYDM_INIT_SUCCESS = 0, 678 PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1 679 }; 680 681 struct phydm_pause_lv { 682 s8 lv_dig; 683 s8 lv_cckpd; 684 s8 lv_antdiv; 685 s8 lv_adapt; 686 s8 lv_adsl; 687 }; 688 689 struct phydm_func_poiner { 690 void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); 691 }; 692 693 struct pkt_process_info { 694 #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH 695 /*@send phystatus in each sampling time*/ 696 boolean physts_auto_swch_en; 697 u8 mac_ppdu_cnt; 698 u8 phy_ppdu_cnt; /*change with phy cca cnt*/ 699 u8 page_bitmap_target; 700 u8 page_bitmap_record; 701 u8 ppdu_phy_rate; 702 u8 ppdu_macid; 703 boolean is_1st_mpdu; 704 #endif 705 u8 lna_idx; 706 u8 vga_idx; 707 }; 708 709 #ifdef ODM_CONFIG_BT_COEXIST 710 struct phydm_bt_info { 711 boolean is_bt_enabled; /*@BT is enabled*/ 712 boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ 713 u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ 714 boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ 715 boolean is_bt_limited_dig; /*@BT is busy.*/ 716 }; 717 #endif 718 719 struct phydm_iot_center { 720 boolean is_linked_cmw500; 721 u8 win_patch_id; /*Customer ID*/ 722 boolean patch_id_100f0401; 723 boolean patch_id_10120200; 724 boolean patch_id_40010700; 725 boolean patch_id_021f0800; 726 u32 phydm_patch_id; /*temp for CCX IOT */ 727 }; 728 729 #if (RTL8822B_SUPPORT) 730 struct drp_rtl8822b_struct { 731 enum bb_path path_judge; 732 u16 path_a_cck_fa; 733 u16 path_b_cck_fa; 734 }; 735 #endif 736 737 #ifdef CONFIG_MCC_DM 738 #define MCC_DM_REG_NUM 32 739 struct _phydm_mcc_dm_ { 740 u8 mcc_pre_status; 741 u8 mcc_reg_id[MCC_DM_REG_NUM]; 742 u16 mcc_dm_reg[MCC_DM_REG_NUM]; 743 u8 mcc_dm_val[MCC_DM_REG_NUM][2]; 744 /*mcc DIG*/ 745 u8 mcc_rssi[2]; 746 /*u8 mcc_igi[2];*/ 747 748 /* need to be config by driver*/ 749 u8 mcc_status; 750 u8 sta_macid[2][NUM_STA]; 751 u16 mcc_rf_ch[2]; 752 753 }; 754 #endif 755 756 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 757 struct phydm_physts { 758 u8 cck_gi_u_bnd; 759 u8 cck_gi_l_bnd; 760 }; 761 #endif 762 763 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 764 #if (RT_PLATFORM != PLATFORM_LINUX) 765 typedef 766 #endif 767 768 struct dm_struct { 769 #else/*for AP, CE Team*/ 770 struct dm_struct { 771 #endif 772 /*@Add for different team use temporarily*/ 773 void *adapter; /*@For CE/NIC team*/ 774 struct rtl8192cd_priv *priv; /*@For AP team*/ 775 boolean odm_ready; 776 enum phy_reg_pg_type phy_reg_pg_value_type; 777 u8 phy_reg_pg_version; 778 u64 support_ability; /*@PHYDM function Supportability*/ 779 u64 pause_ability; /*@PHYDM function pause Supportability*/ 780 u64 debug_components; 781 u8 cmn_dbg_msg_period; 782 u8 cmn_dbg_msg_cnt; 783 u32 fw_debug_components; 784 u32 num_qry_phy_status_all; /*@CCK + OFDM*/ 785 u32 last_num_qry_phy_status_all; 786 u32 rx_pwdb_ave; 787 boolean is_init_hw_info_by_rfe; 788 789 //TSSI 790 u8 en_tssi_mode; 791 792 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 793 boolean is_cck_high_power; 794 u8 rf_path_rx_enable; 795 /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ 796 797 /* @COMMON INFORMATION */ 798 799 /*@Init value*/ 800 /*@-----------HOOK BEFORE REG INIT-----------*/ 801 802 u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ 803 u8 normal_rx_path; 804 u8 valid_path_set; /*@use for single rx path only*/ 805 boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ 806 u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ 807 u32 support_ic_type; /*@PHYDM supported IC*/ 808 enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/ 809 u8 ic_ip_series; /*N/AC/JGR3*/ 810 enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/ 811 u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ 812 u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ 813 u8 fw_version; 814 u8 fw_sub_version; 815 u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ 816 u8 rfe_type; 817 u8 board_type; 818 u8 package_type; 819 u16 type_glna; 820 u16 type_gpa; 821 u16 type_alna; 822 u16 type_apa; 823 u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ 824 u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ 825 u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ 826 u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ 827 u8 efuse0x3d7; /*@with Efuse number*/ 828 u8 efuse0x3d8; 829 u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ 830 u8 ext_lna_gain; /*@gain of external lna*/ 831 boolean is_in_hct_test; 832 u8 wifi_test; 833 boolean is_dual_mac_smart_concurrent; 834 u32 bk_support_ability; /*SD4 only*/ 835 u8 with_extenal_ant_switch; 836 /*@cck agc relative*/ 837 boolean cck_new_agc; 838 s8 cck_lna_gain_table[8]; 839 u8 cck_sat_cnt_th_init; 840 /*@-------------------------------------*/ 841 u32 phydm_sys_up_time; 842 u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ 843 u32 soft_ap_special_setting; 844 boolean boolean_dummy; 845 s8 s8_dummy; 846 u8 u8_dummy; 847 u16 u16_dummy; 848 u32 u32_dummy; 849 u8 rfe_hwsetting_band; 850 u8 p_advance_ota; 851 boolean hp_hw_id; 852 boolean BOOLEAN_temp; 853 boolean is_dfs_band; 854 u8 is_rx_blocking_en; 855 u16 fw_offload_ability; 856 boolean is_download_fw; 857 boolean en_dis_dpd; 858 u16 dis_dpd_rate; 859 u8 en_auto_bw_th; 860 #if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT) 861 u8 txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX]; 862 u32 bp_0x9b0; 863 #endif 864 #if (RTL8822C_SUPPORT) 865 u8 ofdm_rxagc_l_bnd[16]; 866 boolean l_bnd_detect[16]; 867 #endif 868 boolean rf_write_no_protection; 869 /*@-----------HOOK BEFORE REG INIT-----------*/ 870 /*@===========================================================*/ 871 /*@====[ CALL BY Reference ]=========================================*/ 872 /*@===========================================================*/ 873 874 u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ 875 u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ 876 u8 *band_type; /*@2.4G/5G = 0/1*/ 877 u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ 878 u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ 879 u8 *band_width; /*@20M/40M/80M = 0/1/2*/ 880 u8 *channel; /*@central CH number*/ 881 boolean *is_scan_in_process; 882 boolean *is_power_saving; 883 boolean *is_tdma; 884 u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ 885 u8 *antenna_test; 886 boolean *is_net_closed; 887 boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/ 888 /*@--------- For 8723B IQK-------------------------------------*/ 889 boolean *is_1_antenna; 890 u8 *rf_default_path; /* @0:S1, 1:S0 */ 891 /*@-----------------------------------------------------------*/ 892 893 u16 *forced_data_rate; 894 u8 *enable_antdiv; 895 u8 *enable_pathdiv; 896 u8 *en_adap_soml; 897 u8 *edcca_mode; 898 u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ 899 boolean *is_fw_dw_rsvd_page_in_progress; 900 u32 *current_tx_tp; 901 u32 *current_rx_tp; 902 u8 *sounding_seq; 903 u32 *soft_ap_mode; 904 u8 *mp_mode; 905 u32 *interrupt_mask; 906 u8 *bb_op_mode; 907 u32 *manual_supportability; 908 u8 *dis_dym_bw_indication; 909 /*@===========================================================*/ 910 /*@====[ CALL BY VALUE ]===========================================*/ 911 /*@===========================================================*/ 912 913 u8 disable_phydm_watchdog; 914 boolean is_link_in_process; 915 boolean is_wifi_direct; 916 boolean is_wifi_display; 917 boolean is_linked; 918 boolean pre_is_linked; 919 boolean first_connect; 920 boolean first_disconnect; 921 boolean bsta_state; 922 u8 rssi_min; 923 u8 rssi_min_macid; 924 u8 pre_rssi_min; 925 u8 rssi_max; 926 u8 rssi_max_macid; 927 u8 rssi_min_by_path; 928 boolean is_mp_chip; 929 boolean is_one_entry_only; 930 u32 one_entry_macid; 931 u32 one_entry_tp; 932 u32 pre_one_entry_tp; 933 u8 pre_number_linked_client; 934 u8 number_linked_client; 935 u8 pre_number_active_client; 936 u8 number_active_client; 937 boolean is_disable_phy_api; 938 u8 rssi_a; 939 u8 rssi_b; 940 u8 rssi_c; 941 u8 rssi_d; 942 s8 rxsc_80; 943 s8 rxsc_40; 944 s8 rxsc_20; 945 s8 rxsc_l; 946 u64 rssi_trsw; 947 u64 rssi_trsw_h; 948 u64 rssi_trsw_l; 949 u64 rssi_trsw_iso; 950 u8 tx_ant_status; /*TX path enable*/ 951 u8 rx_ant_status; /*RX path enable*/ 952 #ifdef PHYDM_COMPILE_ABOVE_4SS 953 enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/ 954 #endif 955 #ifdef PHYDM_COMPILE_ABOVE_3SS 956 enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/ 957 #endif 958 #ifdef PHYDM_COMPILE_ABOVE_2SS 959 enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/ 960 #endif 961 enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/ 962 u8 cck_lna_idx; 963 u8 cck_vga_idx; 964 u8 curr_station_id; 965 u8 ofdm_agc_idx[4]; 966 u8 rx_rate; 967 u8 rate_ss; 968 u8 tx_rate; 969 u8 linked_interval; 970 u8 pre_channel; 971 u32 txagc_offset_value_a; 972 boolean is_txagc_offset_positive_a; 973 u32 txagc_offset_value_b; 974 boolean is_txagc_offset_positive_b; 975 u8 ap_total_num; 976 boolean flatness_type; 977 /*@[traffic]*/ 978 u8 traffic_load; 979 u8 pre_traffic_load; 980 u32 tx_tp; /*@Mbps*/ 981 u32 rx_tp; /*@Mbps*/ 982 u32 total_tp; /*@Mbps*/ 983 u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ 984 u64 cur_tx_ok_cnt; 985 u64 cur_rx_ok_cnt; 986 u64 last_tx_ok_cnt; 987 u64 last_rx_ok_cnt; 988 u16 consecutive_idlel_time; /*@unit: second*/ 989 /*@---------------------------*/ 990 boolean is_bb_swing_offset_positive_a; 991 boolean is_bb_swing_offset_positive_b; 992 993 /*@[DIG]*/ 994 boolean MPDIG_2G; /*off MPDIG*/ 995 u8 times_2g; /*@for MP DIG*/ 996 u8 force_igi; /*@for debug*/ 997 998 /*@[TDMA-DIG]*/ 999 u8 tdma_dig_timer_ms; 1000 u8 tdma_dig_state_number; 1001 u8 tdma_dig_low_upper_bond; 1002 u8 force_tdma_low_igi; 1003 u8 force_tdma_high_igi; 1004 u8 fix_expire_to_zero; 1005 boolean original_dig_restore; 1006 /*@---------------------------*/ 1007 1008 /*@[AntDiv]*/ 1009 u8 ant_div_type; 1010 u8 antdiv_rssi; 1011 u8 fat_comb_a; 1012 u8 fat_comb_b; 1013 u8 antdiv_intvl; 1014 u8 antdiv_delay; 1015 u8 ant_type; 1016 u8 ant_type2; 1017 u8 pre_ant_type; 1018 u8 pre_ant_type2; 1019 u8 antdiv_period; 1020 u8 evm_antdiv_period; 1021 u8 antdiv_select; 1022 u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ 1023 u8 stop_antdiv_rssi_th; 1024 u16 stop_antdiv_tp_diff_th; 1025 u16 stop_antdiv_tp_th; 1026 u8 antdiv_tp_period; 1027 u16 tp_active_th; 1028 u8 tp_active_occur; 1029 u8 path_select; 1030 u8 antdiv_evm_en; 1031 u8 bdc_holdstate; 1032 u8 antdiv_counter; 1033 /*@---------------------------*/ 1034 1035 u8 ndpa_period; 1036 boolean h2c_rarpt_connect; 1037 boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ 1038 u8 print_agc; 1039 u8 la_mode; 1040 /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ 1041 u8 current_rf_set_8821c; 1042 u8 default_rf_set_8821c; 1043 u8 current_ant_num_8821c; 1044 u8 default_ant_num_8821c; 1045 u8 rfe_type_expand; 1046 /*@-----------------------------------------------------------*/ 1047 /*@---For Adaptivtiy---------------------------------------------*/ 1048 s8 TH_L2H_default; 1049 s8 th_edcca_hl_diff_default; 1050 s8 th_l2h_ini; 1051 s8 th_edcca_hl_diff; 1052 boolean carrier_sense_enable; 1053 /*@-----------------------------------------------------------*/ 1054 u8 pre_dbg_priority; 1055 u8 nbi_set_result; 1056 u8 c2h_cmd_start; 1057 u8 fw_debug_trace[60]; 1058 u8 pre_c2h_seq; 1059 boolean fw_buff_is_enpty; 1060 u32 data_frame_num; 1061 /*@--- for spur detection ---------------------------------------*/ 1062 boolean en_reg_mntr_bb; 1063 boolean en_reg_mntr_rf; 1064 boolean en_reg_mntr_mac; 1065 boolean en_reg_mntr_byte; 1066 /*@--------------------------------------------------------------*/ 1067 #if (RTL8814B_SUPPORT || RTL8812F_SUPPORT) 1068 /*@--- for spur detection ---------------------------------------*/ 1069 u8 dsde_sel; 1070 u8 nbi_path_sel; 1071 u8 csi_wgt; 1072 /*@------------------------------------------*/ 1073 #endif 1074 /*@--- for noise detection ---------------------------------------*/ 1075 boolean is_noisy_state; 1076 boolean noisy_decision; /*@b_noisy*/ 1077 boolean pre_b_noisy; 1078 u32 noisy_decision_smooth; 1079 /*@-----------------------------------------------------------*/ 1080 1081 /*@--- for MCC ant weighting ------------------------------------*/ 1082 boolean is_stop_dym_ant_weighting; 1083 /*@-----------------------------------------------------------*/ 1084 1085 boolean is_disable_dym_ecs; 1086 boolean is_disable_dym_ant_weighting; 1087 struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; 1088 u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ 1089 1090 #if (RATE_ADAPTIVE_SUPPORT) 1091 u16 currmin_rpt_time; 1092 struct _phydm_txstatistic_ hw_stats; 1093 struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; 1094 /*Use mac_id as array index. STA mac_id=0*/ 1095 /*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ 1096 #endif 1097 /*@2012/02/14 MH Add to share 88E ra with other SW team*/ 1098 /*We need to colelct all support abilit to a proper area.*/ 1099 boolean ra_support88e; 1100 boolean *is_driver_stopped; 1101 boolean *is_driver_is_going_to_pnp_set_power_sleep; 1102 boolean *pinit_adpt_in_progress; 1103 boolean is_user_assign_level; 1104 u8 RSSI_BT; /*@come from BT*/ 1105 1106 /*@---PSD Relative ---------------------------------------------*/ 1107 boolean is_psd_in_process; 1108 boolean is_psd_active; 1109 /*@-----------------------------------------------------------*/ 1110 1111 boolean bsomlenabled; /* @D-SoML control */ 1112 u8 no_ndp_cnts; 1113 u8 ndp_cnt_pre; 1114 boolean is_beamformed; 1115 u8 linked_bf_support; 1116 boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ 1117 u32 n_iqk_cnt; 1118 u32 n_iqk_ok_cnt; 1119 u32 n_iqk_fail_cnt; 1120 1121 #if (DM_ODM_SUPPORT_TYPE & ODM_AP) 1122 boolean config_bbrf; 1123 #endif 1124 boolean is_disable_power_training; 1125 boolean is_bt_continuous_turn; 1126 u8 enhance_pwr_th[3]; 1127 u8 set_pwr_th[3]; 1128 /*@----------Dyn Tx Pwr ---------------------------------------*/ 1129 #ifdef BB_RAM_SUPPORT 1130 struct phydm_bb_ram_ctrl p_bb_ram_ctrl; 1131 #endif 1132 u8 dynamic_tx_high_power_lvl; 1133 void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); 1134 u8 last_dtp_lvl; 1135 u8 min_power_index; 1136 u32 tx_agc_ofdm_18_6; 1137 /*-------------------------------------------------------------*/ 1138 u8 rx_pkt_type; 1139 1140 #ifdef CONFIG_PHYDM_DFS_MASTER 1141 u8 dfs_region_domain; 1142 u8 *dfs_master_enabled; 1143 /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ 1144 u8 radar_detect_dbg_parm_en; 1145 u32 radar_detect_reg_918; 1146 u32 radar_detect_reg_91c; 1147 u32 radar_detect_reg_920; 1148 u32 radar_detect_reg_924; 1149 1150 u32 radar_detect_reg_a40; 1151 u32 radar_detect_reg_a44; 1152 u32 radar_detect_reg_a48; 1153 u32 radar_detect_reg_a4c; 1154 u32 radar_detect_reg_a50; 1155 u32 radar_detect_reg_a54; 1156 1157 u32 radar_detect_reg_f54; 1158 u32 radar_detect_reg_f58; 1159 u32 radar_detect_reg_f5c; 1160 u32 radar_detect_reg_f70; 1161 u32 radar_detect_reg_f74; 1162 /*@---For zero-wait DFS---------------------------------------*/ 1163 boolean seg1_dfs_flag; 1164 /*@-----------------------------------------------------------*/ 1165 /*@-----------------------------------------------------------*/ 1166 #endif 1167 1168 /*@=== RTL8721D ===*/ 1169 #if (RTL8721D_SUPPORT) 1170 boolean cbw20_adc80; 1171 boolean invalid_mode; 1172 u8 power_voltage; 1173 u8 cca_cbw20_lev; 1174 u8 cca_cbw40_lev; 1175 u8 antdiv_gpio; 1176 u8 peak_detect_mode; 1177 #endif 1178 1179 /*@=== PHYDM Timer ========================================== (start)*/ 1180 1181 struct phydm_timer_list mpt_dig_timer; 1182 struct phydm_timer_list fast_ant_training_timer; 1183 #ifdef ODM_EVM_ENHANCE_ANTDIV 1184 struct phydm_timer_list evm_fast_ant_training_timer; 1185 #endif 1186 #ifdef PHYDM_TDMA_DIG_SUPPORT 1187 struct phydm_timer_list tdma_dig_timer; 1188 #endif 1189 struct phydm_timer_list sbdcnt_timer; 1190 1191 /*@=== PHYDM Workitem ======================================= (start)*/ 1192 1193 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1194 #if USE_WORKITEM 1195 RT_WORK_ITEM fast_ant_training_workitem; 1196 RT_WORK_ITEM ra_rpt_workitem; 1197 RT_WORK_ITEM sbdcnt_workitem; 1198 RT_WORK_ITEM phydm_evm_antdiv_workitem; 1199 #ifdef PHYDM_TDMA_DIG_SUPPORT 1200 RT_WORK_ITEM phydm_tdma_dig_workitem; 1201 #endif 1202 #endif 1203 #endif 1204 1205 /*@=== PHYDM Structure ======================================== (start)*/ 1206 struct phydm_func_poiner phydm_func_handler; 1207 struct phydm_iot_center iot_table; 1208 1209 #ifdef ODM_CONFIG_BT_COEXIST 1210 struct phydm_bt_info bt_info_table; 1211 #endif 1212 1213 struct pkt_process_info pkt_proc_struct; 1214 struct phydm_adaptivity_struct adaptivity; 1215 #ifdef CONFIG_PHYDM_DFS_MASTER 1216 struct _DFS_STATISTICS dfs; 1217 #endif 1218 struct odm_noise_monitor noise_level; 1219 struct odm_phy_dbg_info phy_dbg_info; 1220 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1221 struct odm_phy_dbg_info phy_dbg_info_win_bkp; 1222 #endif 1223 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT 1224 struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3; 1225 #endif 1226 1227 #ifdef CONFIG_ADAPTIVE_SOML 1228 struct adaptive_soml dm_soml_table; 1229 #endif 1230 1231 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 1232 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 1233 struct _BF_DIV_COEX_ dm_bdc_table; 1234 #endif 1235 1236 #if (defined(CONFIG_HL_SMART_ANTENNA)) 1237 struct smt_ant_honbo dm_sat_table; 1238 #endif 1239 #endif 1240 1241 #if (defined(CONFIG_SMART_ANTENNA)) 1242 struct smt_ant smtant_table; 1243 #endif 1244 1245 struct _hal_rf_ rf_table; /*@for HALRF function*/ 1246 struct dm_rf_calibration_struct rf_calibrate_info; 1247 struct dm_iqk_info IQK_info; 1248 struct dm_dpk_info dpk_info; 1249 struct dm_dack_info dack_info; 1250 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY 1251 struct phydm_fat_struct dm_fat_table; 1252 struct sw_antenna_switch dm_swat_table; 1253 #endif 1254 struct phydm_dig_struct dm_dig_table; 1255 1256 #ifdef PHYDM_SUPPORT_CCKPD 1257 struct phydm_cckpd_struct dm_cckpd_table; 1258 1259 #ifdef PHYDM_DCC_ENHANCE 1260 struct phydm_dcc_struct dm_dcc_info; /*dig cckpd coex*/ 1261 #endif 1262 #endif 1263 1264 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT 1265 struct phydm_lna_sat_t dm_lna_sat_info; 1266 #endif 1267 1268 #ifdef CONFIG_MCC_DM 1269 struct _phydm_mcc_dm_ mcc_dm; 1270 #endif 1271 1272 #ifdef PHYDM_PRIMARY_CCA 1273 struct phydm_pricca_struct dm_pri_cca; 1274 #endif 1275 1276 struct ra_table dm_ra_table; 1277 struct phydm_fa_struct false_alm_cnt; 1278 #ifdef PHYDM_TDMA_DIG_SUPPORT 1279 struct phydm_fa_acc_struct false_alm_cnt_acc; 1280 #ifdef IS_USE_NEW_TDMA 1281 struct phydm_fa_acc_struct false_alm_cnt_acc_low; 1282 #endif 1283 #endif 1284 struct phydm_cfo_track_struct dm_cfo_track; 1285 struct ccx_info dm_ccx_info; 1286 1287 struct odm_power_trim_data power_trim_data; 1288 #if (RTL8822B_SUPPORT) 1289 struct drp_rtl8822b_struct phydm_rtl8822b; 1290 #endif 1291 1292 #ifdef CONFIG_PSD_TOOL 1293 struct psd_info dm_psd_table; 1294 #endif 1295 1296 #if (PHYDM_LA_MODE_SUPPORT) 1297 struct rt_adcsmp adcsmp; 1298 #endif 1299 1300 #if (defined(CONFIG_PATH_DIVERSITY)) 1301 struct _ODM_PATH_DIVERSITY_ dm_path_div; 1302 #endif 1303 1304 #if (defined(CONFIG_ANT_DETECTION)) 1305 struct _ANT_DETECTED_INFO ant_detected_info; 1306 #endif 1307 1308 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 1309 #ifdef PHYDM_BEAMFORMING_SUPPORT 1310 struct _RT_BEAMFORMING_INFO beamforming_info; 1311 #endif 1312 #endif 1313 #ifdef PHYDM_AUTO_DEGBUG 1314 struct phydm_auto_dbg_struct auto_dbg_table; 1315 #endif 1316 1317 struct phydm_pause_lv pause_lv_table; 1318 struct phydm_api_stuc api_table; 1319 #ifdef PHYDM_POWER_TRAINING_SUPPORT 1320 struct phydm_pow_train_stuc pow_train_table; 1321 #endif 1322 1323 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT 1324 struct phydm_pmac_tx dm_pmac_tx_table; 1325 #endif 1326 1327 #ifdef PHYDM_MP_SUPPORT 1328 struct phydm_mp dm_mp_table; 1329 #endif 1330 1331 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT 1332 struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table; 1333 #endif 1334 /*@==========================================================*/ 1335 1336 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) 1337 /*@-------------------phydm_phystatus report --------------------*/ 1338 struct phydm_physts dm_physts_table; 1339 #endif 1340 1341 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) 1342 1343 #if (RT_PLATFORM != PLATFORM_LINUX) 1344 } dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ 1345 #else 1346 }; 1347 #endif 1348 1349 #else /*@for AP,CE Team*/ 1350 }; 1351 #endif 1352 1353 enum phydm_adv_ota { 1354 PHYDM_PATHB_1RCCA = BIT(0), 1355 PHYDM_HP_OTA_SETTING_A = BIT(1), 1356 PHYDM_HP_OTA_SETTING_B = BIT(2), 1357 PHYDM_ASUS_OTA_SETTING = BIT(3), 1358 PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), 1359 PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), 1360 PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), 1361 1362 }; 1363 1364 enum phydm_bb_op_mode { 1365 PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ 1366 PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ 1367 }; 1368 1369 enum phydm_structure_type { 1370 PHYDM_FALSEALMCNT, 1371 PHYDM_CFOTRACK, 1372 PHYDM_ADAPTIVITY, 1373 PHYDM_DFS, 1374 PHYDM_ROMINFO, 1375 1376 }; 1377 1378 enum odm_bb_config_type { 1379 CONFIG_BB_PHY_REG, 1380 CONFIG_BB_AGC_TAB, 1381 CONFIG_BB_AGC_TAB_2G, 1382 CONFIG_BB_AGC_TAB_5G, 1383 CONFIG_BB_PHY_REG_PG, 1384 CONFIG_BB_PHY_REG_MP, 1385 CONFIG_BB_AGC_TAB_DIFF, 1386 CONFIG_BB_RF_CAL_INIT, 1387 }; 1388 1389 enum odm_rf_config_type { 1390 CONFIG_RF_RADIO, 1391 CONFIG_RF_TXPWR_LMT, 1392 CONFIG_RF_SYN_RADIO, 1393 }; 1394 1395 enum odm_fw_config_type { 1396 CONFIG_FW_NIC, 1397 CONFIG_FW_NIC_2, 1398 CONFIG_FW_AP, 1399 CONFIG_FW_AP_2, 1400 CONFIG_FW_MP, 1401 CONFIG_FW_WOWLAN, 1402 CONFIG_FW_WOWLAN_2, 1403 CONFIG_FW_AP_WOWLAN, 1404 CONFIG_FW_BT, 1405 }; 1406 1407 /*status code*/ 1408 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) 1409 enum rt_status { 1410 RT_STATUS_SUCCESS, 1411 RT_STATUS_FAILURE, 1412 RT_STATUS_PENDING, 1413 RT_STATUS_RESOURCE, 1414 RT_STATUS_INVALID_CONTEXT, 1415 RT_STATUS_INVALID_PARAMETER, 1416 RT_STATUS_NOT_SUPPORT, 1417 RT_STATUS_OS_API_FAILED, 1418 }; 1419 #endif /*@end of enum rt_status definition*/ 1420 1421 void 1422 phydm_watchdog_lps(struct dm_struct *dm); 1423 1424 void 1425 phydm_watchdog_lps_32k(struct dm_struct *dm); 1426 1427 void 1428 phydm_txcurrentcalibration(struct dm_struct *dm); 1429 1430 void 1431 phydm_dm_early_init(struct dm_struct *dm); 1432 1433 enum phydm_init_result 1434 odm_dm_init(struct dm_struct *dm); 1435 1436 void 1437 odm_dm_reset(struct dm_struct *dm); 1438 1439 void 1440 phydm_fwoffload_ability_init(struct dm_struct *dm, 1441 enum phydm_offload_ability offload_ability); 1442 1443 void 1444 phydm_fwoffload_ability_clear(struct dm_struct *dm, 1445 enum phydm_offload_ability offload_ability); 1446 1447 void 1448 phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, 1449 char *output, u32 *_out_len); 1450 1451 void 1452 phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); 1453 1454 void 1455 phydm_watchdog(struct dm_struct *dm); 1456 1457 void 1458 phydm_watchdog_mp(struct dm_struct *dm); 1459 1460 void 1461 phydm_pause_func_init(void *dm_void); 1462 1463 u8 1464 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, 1465 enum phydm_pause_type pause_type, 1466 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); 1467 1468 void 1469 phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, 1470 char *output, u32 *_out_len); 1471 1472 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm, 1473 enum phydm_pause_type pause_type, u8 rssi); 1474 1475 void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx, 1476 boolean enable); 1477 1478 void 1479 odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); 1480 1481 void 1482 odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); 1483 1484 void 1485 odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); 1486 1487 u32 1488 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); 1489 1490 void 1491 odm_init_all_timers(struct dm_struct *dm); 1492 1493 void 1494 odm_cancel_all_timers(struct dm_struct *dm); 1495 1496 void 1497 odm_release_all_timers(struct dm_struct *dm); 1498 1499 void * 1500 phydm_get_structure(struct dm_struct *dm, u8 structure_type); 1501 1502 void 1503 phydm_dc_cancellation(struct dm_struct *dm); 1504 1505 void 1506 phydm_receiver_blocking(void *dm_void); 1507 1508 void 1509 phydm_dyn_bw_indication(void *dm_void); 1510 1511 void 1512 phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en); 1513 1514 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 1515 void 1516 odm_init_all_work_items( 1517 struct dm_struct *dm 1518 ); 1519 void 1520 odm_free_all_work_items( 1521 struct dm_struct *dm 1522 ); 1523 #endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ 1524 1525 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 1526 void 1527 odm_dtc(struct dm_struct *dm); 1528 #endif 1529 1530 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 1531 void 1532 odm_init_all_threads( 1533 struct dm_struct *dm 1534 ); 1535 1536 void 1537 odm_stop_all_threads( 1538 struct dm_struct *dm 1539 ); 1540 #endif 1541 1542 #endif 1543