Searched refs:reset_stat_bit (Results 1 – 2 of 2) sorted by relevance
7303 bool reset_stat_bit; in dhd_bus_cfg_ss_ctrl_bp_reset() local7338 reset_stat_bit = val & (1 << PCIE_CFG_SUBSYSTEM_CONTROL_BP_RESET_STATUS_BIT); in dhd_bus_cfg_ss_ctrl_bp_reset()7340 } while (!reset_stat_bit && (retry++ < DHD_BP_RESET_STATUS_RETRIES)); in dhd_bus_cfg_ss_ctrl_bp_reset()7342 if (!reset_stat_bit) { in dhd_bus_cfg_ss_ctrl_bp_reset()7368 reset_stat_bit = val & (1 << PCIE_CFG_SUBSYSTEM_CONTROL_BP_RESET_STATUS_BIT); in dhd_bus_cfg_ss_ctrl_bp_reset()7370 } while (reset_stat_bit && (retry++ < DHD_BP_RESET_STATUS_RETRIES)); in dhd_bus_cfg_ss_ctrl_bp_reset()7372 if (reset_stat_bit) { in dhd_bus_cfg_ss_ctrl_bp_reset()
7296 bool reset_stat_bit; in dhd_bus_cfg_ss_ctrl_bp_reset() local7331 reset_stat_bit = val & (1 << PCIE_CFG_SUBSYSTEM_CONTROL_BP_RESET_STATUS_BIT); in dhd_bus_cfg_ss_ctrl_bp_reset()7333 } while (!reset_stat_bit && (retry++ < DHD_BP_RESET_STATUS_RETRIES)); in dhd_bus_cfg_ss_ctrl_bp_reset()7335 if (!reset_stat_bit) { in dhd_bus_cfg_ss_ctrl_bp_reset()7361 reset_stat_bit = val & (1 << PCIE_CFG_SUBSYSTEM_CONTROL_BP_RESET_STATUS_BIT); in dhd_bus_cfg_ss_ctrl_bp_reset()7363 } while (reset_stat_bit && (retry++ < DHD_BP_RESET_STATUS_RETRIES)); in dhd_bus_cfg_ss_ctrl_bp_reset()7365 if (reset_stat_bit) { in dhd_bus_cfg_ss_ctrl_bp_reset()