Searched refs:regs_set (Results 1 – 7 of 7) sorted by relevance
78 HalVepu540cRegSet *regs_set; member135 MPP_FREE(p->regs_set); in hal_h264e_vepu540c_deinit()178 p->regs_set = mpp_calloc(HalVepu540cRegSet, 1); in hal_h264e_vepu540c_init()180 if (!p->regs_set) { in hal_h264e_vepu540c_init()1515 HalVepu540cRegSet *regs = ctx->regs_set; in hal_h264e_vepu540c_gen_regs()1549 setup_vepu540c_l2(ctx->regs_set, slice, &cfg->hw); in hal_h264e_vepu540c_gen_regs()1553 vepu540c_set_roi(&ctx->regs_set->reg_rc_roi.roi_cfg, ctx->roi_data, in hal_h264e_vepu540c_gen_regs()1589 wr_cfg.reg = &ctx->regs_set->reg_ctl; in hal_h264e_vepu540c_start()1590 wr_cfg.size = sizeof(ctx->regs_set->reg_ctl); in hal_h264e_vepu540c_start()1596 for ( i = 0; i < sizeof(ctx->regs_set->reg_ctl) / sizeof(RK_U32); i++) { in hal_h264e_vepu540c_start()[all …]
117 HalVepu580RegSet *regs_set; member578 ctx->regs_set = &ctx->regs_sets[ctx->task_idx]; in hal_h264e_vepu580_get_task()580 ctx->osd_cfg.reg_base = &ctx->regs_set->reg_osd; in hal_h264e_vepu580_get_task()2161 Vepu580BaseCfg *reg_base = &ctx->regs_set->reg_base; in setup_vepu580_dual_core()2190 HalVepu580RegSet *regs = ctx->regs_set; in hal_h264e_vepu580_gen_regs()2270 HalVepu580RegSet *regs = ctx->regs_set; in hal_h264e_vepu580_start()
84 Vepu541H264eRegSet regs_set; member191 p->osd_cfg.reg_base = &p->regs_set; in hal_h264e_vepu541_init()1547 Vepu541H264eRegSet *regs = &ctx->regs_set; in hal_h264e_vepu541_gen_regs()1641 wr_cfg.reg = &ctx->regs_set; in hal_h264e_vepu541_start()
141 HalVepu580RegSet *regs = ctx->regs_set; in vepu580_h264e_tune_reg_patch()
101 static int regs_set(struct task_struct *target, in regs_set() function138 .set = regs_set,
76 H264eVpu2RegSet regs_set; member291 RK_U32 *reg = ctx->regs_set.val; in setup_intra_refresh()347 RK_U32 *reg = ctx->regs_set.val; in hal_h264e_vepu2_gen_regs_v2()653 RK_U32 reg_size = sizeof(ctx->regs_set); in hal_h264e_vepu2_start_v2()656 wr_cfg.reg = &ctx->regs_set; in hal_h264e_vepu2_start_v2()
76 H264eVpu1RegSet regs_set; member297 RK_U32 *reg = ctx->regs_set.val; in hal_h264e_vepu1_gen_regs_v2()588 RK_U32 reg_size = sizeof(ctx->regs_set); in hal_h264e_vepu1_start_v2()591 wr_cfg.reg = &ctx->regs_set; in hal_h264e_vepu1_start_v2()