Searched refs:pll_ddr (Results 1 – 3 of 3) sorted by relevance
156 reg = readl(&ccm_anatop->pll_ddr); in decode_pll()345 reg = readl(&ccm_anatop->pll_ddr); in mxc_get_pll_ddr_derive()
229 pll_ddr: clk-pll-932m { label233 clock-output-names = "pll_ddr";
91 uint32_t pll_ddr; /* offset 0x0070 */ member