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Searched refs:pipe_dlg_param (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/calcs/
H A Ddcn_calcs.c445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; in pipe_ctx_to_e2e_pipe_params()
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; in pipe_ctx_to_e2e_pipe_params()
1224 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; in dcn_validate_bandwidth()
1225 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; in dcn_validate_bandwidth()
1226 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; in dcn_validate_bandwidth()
1227 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1229 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
1230 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hwseq.c700 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_enable_stream_timing()
701 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_enable_stream_timing()
702 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn20_enable_stream_timing()
703 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn20_enable_stream_timing()
1275 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset in dcn20_detect_pipe_changes()
1276 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start in dcn20_detect_pipe_changes()
1277 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset in dcn20_detect_pipe_changes()
1278 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) in dcn20_detect_pipe_changes()
1396 &pipe_ctx->pipe_dlg_param); in dcn20_update_dchubp_dpp()
1582 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_program_pipe()
[all …]
H A Ddcn20_resource.c3106 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c816 pipe_ctx->pipe_dlg_param.vready_offset, in dcn10_enable_stream_timing()
817 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_enable_stream_timing()
818 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_enable_stream_timing()
819 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn10_enable_stream_timing()
2548 &pipe_ctx->pipe_dlg_param); in dcn10_update_dchubp_dpp()
2733 pipe_ctx->pipe_dlg_param.vready_offset, in dcn10_program_all_pipe_in_tree()
2734 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_program_all_pipe_in_tree()
2735 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_program_all_pipe_in_tree()
2736 pipe_ctx->pipe_dlg_param.vupdate_width); in dcn10_program_all_pipe_in_tree()
3601 pipe_ctx->pipe_dlg_param.vstartup_start + 1; in dcn10_get_vupdate_offset_from_vsync()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h330 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; member