Home
last modified time | relevance | path

Searched refs:pic_width_in_mbs (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/staging/media/tegra-vde/
H A Dvde.c339 ctx->pic_width_in_mbs, ctx->pic_height_in_mbs); in tegra_vde_setup_hw_context()
355 value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3; in tegra_vde_setup_hw_context()
389 value |= ctx->pic_width_in_mbs << 11; in tegra_vde_setup_hw_context()
428 value |= ctx->pic_width_in_mbs << 11; in tegra_vde_setup_hw_context()
677 if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) { in tegra_vde_validate_h264_ctx()
679 ctx->pic_width_in_mbs); in tegra_vde_validate_h264_ctx()
743 macroblocks_nb = ctx.pic_width_in_mbs * ctx.pic_height_in_mbs; in tegra_vde_ioctl_decode_h264()
752 cstride = ALIGN(ctx.pic_width_in_mbs * 8, 16); in tegra_vde_ioctl_decode_h264()
H A Duapi.h43 __u32 pic_width_in_mbs; member
/OK3568_Linux_fs/kernel/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_h264.c332 unsigned int pic_width_in_mbs; in cedrus_set_params() local
416 pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1; in cedrus_set_params()
420 reg |= ((slice->first_mb_in_slice % pic_width_in_mbs) & 0xff) << 24; in cedrus_set_params()
421 reg |= (((slice->first_mb_in_slice / pic_width_in_mbs) * in cedrus_set_params()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu2_v2.c287 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in setup_intra_refresh()
348 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu2_gen_regs_v2()
357 mb_h = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu2_gen_regs_v2()
761 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu2_ret_task_v2()
H A Dhal_h264e_vepu1_v2.c298 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu1_gen_regs_v2()
307 mb_h = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu1_gen_regs_v2()
696 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu1_ret_task_v2()
/OK3568_Linux_fs/external/mpp/mpp/codec/enc/h264/
H A Dh264e_sps.h106 RK_S32 pic_width_in_mbs; member
H A Dh264e_sps.c199 sps->pic_width_in_mbs = aligned_w >> 4; in h264e_sps_update()
329 mpp_writer_put_ue(bit, sps->pic_width_in_mbs - 1); in h264e_sps_to_packet()
H A Dh264e_slice.c48 slice->mb_w = sps->pic_width_in_mbs; in h264e_slice_update()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c800 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu541_rc_base()
973 RK_U32 w = ctx->sps->pic_width_in_mbs * 16; in setup_vepu541_intra_refresh()
1075 RK_U32 w = ctx->sps->pic_width_in_mbs * 16; in setup_vepu541_roi()
1237 RK_S32 pic_w = sps->pic_width_in_mbs * 16; in setup_vepu541_me()
1275 if (cime_blk_w_max / 4 * 2 > (sps->pic_width_in_mbs * 2 + 1) / 2) in setup_vepu541_me()
1276 cime_blk_w_max = (sps->pic_width_in_mbs * 2 + 1) / 2 / 2 * 4; in setup_vepu541_me()
1758 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu541_ret_task()
H A Dhal_h264e_vepu580.c1318 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu580_rc_base()
1545 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in setup_vepu580_intra_refresh()
1792 RK_S32 pic_wd64 = MPP_ALIGN(sps->pic_width_in_mbs * 16, 64) / 64; in calc_cime_parameter()
1909 if (cime_blk_w_max / 4 * 2 > (sps->pic_width_in_mbs * 2 + 1) / 2) in setup_vepu580_me()
1910 cime_blk_w_max = (sps->pic_width_in_mbs * 2 + 1) / 2 / 2 * 4; in setup_vepu580_me()
2532 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu580_ret_task()
H A Dhal_h264e_vepu540c.c963 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu540c_rc_base()
1735 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu540c_ret_task()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_base.h114 RK_S32 pic_width_in_mbs; member
H A Dhal_vp8e_base.c1017 sps->pic_width_in_mbs = width_align / 16; in set_parameter()
1163 RK_S32 width = ctx->sps.pic_width_in_mbs * 16; in set_picbuf()