Searched refs:pdiv3 (Results 1 – 3 of 3) sorted by relevance
38 u32 pdiv3; member
99 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3); in setup_clock_synthesizer()
606 .pdiv3 = 0x2,662 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ in board_init()