| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_mpc.c | 345 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc1_init_mpcc() argument
347 mpcc->mpcc_id = mpcc_inst; in mpc1_init_mpcc()
453 int mpcc_inst, in mpc1_read_mpcc_state() argument
458 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
459 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc1_read_mpcc_state()
460 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc1_read_mpcc_state()
461 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc1_read_mpcc_state()
465 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc1_read_mpcc_state()
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| H A D | dcn10_hw_sequencer.c | 1066 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1237 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn10_init_pipes()
1244 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
3254 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
3259 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
3272 int mpcc_inst; in dcn10_wait_for_mpcc_disconnect() local
3281 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
3282 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { in dcn10_wait_for_mpcc_disconnect()
3283 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
3285 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
[all …]
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| H A D | dcn10_mpc.h | 198 int mpcc_inst,
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| H A D | dcn10_resource.c | 1175 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_hwseq.c | 227 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
228 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
234 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
249 wb_info->mpcc_inst); in dcn30_update_writeback()
331 wb_info->mpcc_inst); in dcn30_enable_writeback()
395 wb_info.mpcc_inst = -1; in dcn30_program_all_writeback_pipes_in_tree()
403 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
408 if (wb_info.mpcc_inst == -1) { in dcn30_program_all_writeback_pipes_in_tree()
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| H A D | dcn30_mpc.c | 1009 static void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc3_init_mpcc() argument
1011 mpcc->mpcc_id = mpcc_inst; in mpc3_init_mpcc()
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| H A D | dcn30_resource.c | 1868 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_psr.c | 239 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | mpc.h | 163 int mpcc_inst,
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_mpc.c | 513 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
515 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
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| H A D | dcn20_hwseq.c | 1432 int mpcc_inst = hubp->inst; in dcn20_update_dchubp_dpp() local
1437 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { in dcn20_update_dchubp_dpp()
1438 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in dcn20_update_dchubp_dpp()
1439 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in dcn20_update_dchubp_dpp()
2491 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn20_fpga_init_hw()
2501 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
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| H A D | dcn20_resource.c | 1881 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1956 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in dcn20_split_stream_for_mpc()
3284 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 283 uint8_t mpcc_inst; member
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_stream.h | 95 int mpcc_inst; member
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1407 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
1783 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_free_pipe()
2040 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; in acquire_resource_from_hw_enabled_state()
2046 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); in acquire_resource_from_hw_enabled_state()
2049 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = s.dpp_id; in acquire_resource_from_hw_enabled_state()
2052 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = in acquire_resource_from_hw_enabled_state()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 563 uint8_t mpcc_inst; member
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/calcs/ |
| H A D | dcn_calcs.c | 539 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()
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