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Searched refs:mpc_mask (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
166 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
168 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
224 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
226 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
252 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
254 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
256 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
258 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
260 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
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H A Ddcn20_mpc.h267 const struct dcn20_mpc_mask *mpc_mask; member
274 const struct dcn20_mpc_mask *mpc_mask,
H A Ddcn20_resource.c847 static const struct dcn20_mpc_mask mpc_mask = { variable
1218 &mpc_mask, in dcn20_mpc_create()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
170 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
172 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
175 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field()
177 reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
179 reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc3_ogam_get_reg_field()
181 reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
184 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field()
186 reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc3_ogam_get_reg_field()
188 reg->masks.field_region_end_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc3_ogam_get_reg_field()
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H A Ddcn30_mpc.h599 const struct dcn30_mpc_mask *mpc_mask; member
607 const struct dcn30_mpc_mask *mpc_mask,
H A Ddcn30_resource.c680 static const struct dcn30_mpc_mask mpc_mask = { variable
984 &mpc_mask, in dcn30_mpc_create()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
498 const struct dcn_mpc_mask *mpc_mask, in dcn10_mpc_construct() argument
509 mpc10->mpc_mask = mpc_mask; in dcn10_mpc_construct()
H A Ddcn10_mpc.h131 const struct dcn_mpc_mask *mpc_mask; member
138 const struct dcn_mpc_mask *mpc_mask,
H A Ddcn10_resource.c447 static const struct dcn_mpc_mask mpc_mask = { variable
753 &mpc_mask, in dcn10_mpc_create()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c518 static const struct dcn20_mpc_mask mpc_mask = { variable
1372 &mpc_mask, in dcn21_mpc_create()