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Searched refs:mmUVD_STATUS (Results 1 – 19 of 19) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c327 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
381 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
407 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
452 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
495 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop()
697 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
H A Duvd_v4_2.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
263 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
317 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
343 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
388 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
431 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
H A Duvd_v5_0.c213 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
362 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
388 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
450 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
H A Dvcn_v1_0.c239 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
800 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
801 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
872 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
906 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
907 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
1128 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1158 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode()
1342 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1350 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
H A Dvcn_v3_0.c359 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
1063 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v3_0_start()
1064 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start()
1138 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start()
1170 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v3_0_start()
1267 mmUVD_STATUS), in vcn_v3_0_start_sriov()
1476 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
1521 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v3_0_stop()
1822 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle()
1837 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle()
[all …]
H A Dvcn_v2_5.c337 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
937 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
938 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
1021 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1056 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1191 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1346 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1384 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1690 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1704 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()
H A Dvcn_v2_0.c273 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
948 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_0_start()
949 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v2_0_start()
1023 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start()
1054 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v2_0_start()
1145 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1188 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop()
1281 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1289 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()
1874 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in vcn_v2_0_start_sriov()
H A Duvd_v6_0.c545 if (RREG32(mmUVD_STATUS) != 0) in uvd_v6_0_hw_fini()
784 status = RREG32(mmUVD_STATUS); in uvd_v6_0_start()
811 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start()
888 WREG32(mmUVD_STATUS, 0); in uvd_v6_0_stop()
1144 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) in uvd_v6_0_check_soft_reset()
H A Duvd_v7_0.c799 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
889 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
911 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); in uvd_v7_0_sriov_start()
1026 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); in uvd_v7_0_start()
1056 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start()
1462 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
H A Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
H A Duvd_3_1_d.h78 #define mmUVD_STATUS 0x3daf macro
H A Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro
H A Duvd_6_0_d.h98 #define mmUVD_STATUS 0x3daf macro
H A Duvd_7_0_offset.h208 #define mmUVD_STATUS … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h394 #define mmUVD_STATUS … macro
H A Dvcn_2_5_offset.h487 #define mmUVD_STATUS … macro
H A Dvcn_2_0_0_offset.h698 #define mmUVD_STATUS … macro
H A Dvcn_3_0_0_offset.h797 #define mmUVD_STATUS … macro