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Searched refs:mmUVD_RB_WPTR2 (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h43 #define mmUVD_RB_WPTR2 0x3c25 macro
H A Duvd_7_0_offset.h92 #define mmUVD_RB_WPTR2 … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h214 #define mmUVD_RB_WPTR2 … macro
H A Dvcn_2_5_offset.h569 #define mmUVD_RB_WPTR2 … macro
H A Dvcn_2_0_0_offset.h926 #define mmUVD_RB_WPTR2 … macro
H A Dvcn_3_0_0_offset.h899 #define mmUVD_RB_WPTR2 … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c952 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1178 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v1_0_stop_dpg_mode()
1257 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1607 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v1_0_enc_ring_get_wptr()
1625 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, in vcn_v1_0_enc_ring_set_wptr()
H A Dvcn_v2_5.c1098 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1316 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v2_5_stop_dpg_mode()
1453 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1592 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v2_5_enc_ring_get_wptr()
1619 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
H A Dvcn_v2_0.c1095 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1116 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v2_0_stop_dpg_mode()
1251 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1573 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v2_0_enc_ring_get_wptr()
1600 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
H A Dvcn_v3_0.c1206 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1445 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v3_0_stop_dpg_mode()
1584 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1721 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v3_0_enc_ring_get_wptr()
1748 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
H A Duvd_v6_0.c128 return RREG32(mmUVD_RB_WPTR2); in uvd_v6_0_enc_ring_get_wptr()
160 WREG32(mmUVD_RB_WPTR2, in uvd_v6_0_enc_ring_set_wptr()
853 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
H A Duvd_v7_0.c126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in uvd_v7_0_enc_ring_get_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
1101 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()