Searched refs:mmUVD_RB_BASE_HI (Results 1 – 12 of 12) sorted by relevance
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_d.h | 45 #define mmUVD_RB_BASE_HI 0x3c27 macro
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| H A D | uvd_7_0_offset.h | 96 #define mmUVD_RB_BASE_HI … macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 218 #define mmUVD_RB_BASE_HI … macro
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| H A D | vcn_2_5_offset.h | 553 #define mmUVD_RB_BASE_HI … macro
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| H A D | vcn_2_0_0_offset.h | 930 #define mmUVD_RB_BASE_HI … macro
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| H A D | vcn_3_0_0_offset.h | 883 #define mmUVD_RB_BASE_HI … macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v2_5.c | 1091 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1264 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), in vcn_v2_5_sriov_start()
1440 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
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| H A D | vcn_v2_0.c | 1088 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1238 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1947 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), in vcn_v2_0_start_sriov()
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| H A D | vcn_v3_0.c | 1201 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1338 mmUVD_RB_BASE_HI), in vcn_v3_0_start_sriov()
1573 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
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| H A D | vcn_v1_0.c | 947 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
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| H A D | uvd_v7_0.c | 901 …MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_ad… in uvd_v7_0_sriov_start()
1096 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
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| H A D | uvd_v6_0.c | 848 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
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