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Searched refs:mmDPG_WATERMARK_MASK_CONTROL (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_resource.c117 - mmDPG_WATERMARK_MASK_CONTROL),
123 - mmDPG_WATERMARK_MASK_CONTROL),
129 - mmDPG_WATERMARK_MASK_CONTROL),
135 - mmDPG_WATERMARK_MASK_CONTROL),
141 - mmDPG_WATERMARK_MASK_CONTROL),
147 - mmDPG_WATERMARK_MASK_CONTROL),
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1060 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v8_0_program_watermarks()
1064 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_program_watermarks()
1069 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v8_0_program_watermarks()
1072 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_program_watermarks()
1077 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v8_0_program_watermarks()
H A Ddce_v10_0.c1125 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1127 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
H A Ddce_v11_0.c1151 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1153 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1160 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h5180 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
H A Ddce_10_0_d.h6393 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
H A Ddce_11_0_d.h6516 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro
H A Ddce_11_2_d.h7814 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 macro