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Searched refs:mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h653 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h291 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h301 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h282 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … macro