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Searched refs:mmCP_MEM_SLP_CNTL (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c91 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
222 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
H A Dsi.c549 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
646 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
746 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
826 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
903 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
H A Dgfx_v6_0.c2613 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2616 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
2637 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2640 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
H A Dgfx_v8_0.c304 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
467 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
674 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
707 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5506 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5723 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5726 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
H A Dgfx_v7_0.c3631 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3634 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
3684 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3687 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
H A Dgfx_v9_0.c4858 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4861 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4887 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4890 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5190 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
H A Dgfx_v10_0.c7376 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7379 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7393 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7396 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7679 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h455 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_7_0_d.h255 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_7_2_d.h257 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_8_1_d.h289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_8_0_d.h289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2482 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_9_2_1_offset.h2697 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_9_1_offset.h2759 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_10_1_0_offset.h4821 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_10_3_0_offset.h4476 #define mmCP_MEM_SLP_CNTL … macro