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Searched refs:mmCP_HQD_DEQUEUE_REQUEST (Results 1 – 18 of 18) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v8.c481 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
496 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v7.c483 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
498 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v10.c609 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
625 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v9.c573 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); in kgd_gfx_v9_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v10_3.c546 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); in hqd_destroy_v10_3()
H A Dgfx_v9_0.c3588 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_init_register()
3594 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_init_register()
3686 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_fini_register()
3701 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_fini_register()
H A Dgfx_v7_0.c2902 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v7_0_mqd_deactivate()
2912 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v7_0_mqd_deactivate()
H A Dgfx_v10_0.c6542 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v10_0_kiq_init_register()
6548 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v10_0_kiq_init_register()
H A Dgfx_v8_0.c4425 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v8_0_deactivate_hqd()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h591 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
H A Dgfx_7_2_d.h604 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
H A Dgfx_8_1_d.h654 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
H A Dgfx_8_0_d.h654 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2865 #define mmCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_9_2_1_offset.h3049 #define mmCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_9_1_offset.h3093 #define mmCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_10_1_0_offset.h5329 #define mmCP_HQD_DEQUEUE_REQUEST … macro
H A Dgc_10_3_0_offset.h4962 #define mmCP_HQD_DEQUEUE_REQUEST … macro