Searched refs:mg_pll_bias (Results 1 – 4 of 4) sorted by relevance
209 u32 mg_pll_bias; member
3311 pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) | in icl_calc_mg_pll_state()3362 pll_state->mg_pll_bias = in icl_calc_mg_pll_state()3382 pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask; in icl_calc_mg_pll_state()3402 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { in icl_ddi_mg_pll_get_freq()3403 m2_frac = pll_state->mg_pll_bias & in icl_ddi_mg_pll_get_freq()3718 hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()3731 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; in mg_pll_get_hw_state()3798 hw_state->mg_pll_bias = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()3799 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | in dkl_pll_get_hw_state()3946 val |= hw_state->mg_pll_bias; in icl_mg_pll_write()[all …]
961 pll->state.hw_state.mg_pll_bias); in i915_shared_dplls_info()
14017 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); in intel_pipe_config_compare()