Searched refs:me_rnge (Results 1 – 6 of 6) sorted by relevance
1225 srch_lftw = base_regs->me_rnge.cime_srch_lftw * 4; in calc_cime_parameter()1226 srch_rgtw = base_regs->me_rnge.cime_srch_rgtw * 4; in calc_cime_parameter()1227 srch_uph = base_regs->me_rnge.cime_srch_uph * 2; in calc_cime_parameter()1228 srch_dwnh = base_regs->me_rnge.cime_srch_dwnh * 2; in calc_cime_parameter()1305 regs->reg_base.me_rnge.cime_srch_dwnh = 15; in setup_vepu540c_me()1306 regs->reg_base.me_rnge.cime_srch_uph = 14; in setup_vepu540c_me()1307 regs->reg_base.me_rnge.cime_srch_rgtw = 12; in setup_vepu540c_me()1308 regs->reg_base.me_rnge.cime_srch_lftw = 12; in setup_vepu540c_me()1316 regs->reg_base.me_rnge.dlt_frm_num = 0x0; in setup_vepu540c_me()
1599 regs->reg_base.me_rnge.cme_srch_v = 1; in setup_vepu580_intra_refresh()1610 regs->reg_base.me_rnge.cme_srch_h = 1; in setup_vepu580_intra_refresh()1789 RK_S32 srch_w = base_regs->me_rnge.cme_srch_h * 4; in calc_cime_parameter()1790 RK_S32 srch_h = base_regs->me_rnge.cme_srch_v * 4; in calc_cime_parameter()1915 regs->reg_base.me_rnge.cme_srch_h = cime_blk_w_max / 4; in setup_vepu580_me()1916 regs->reg_base.me_rnge.cme_srch_v = cime_blk_h_max / 4; in setup_vepu580_me()1917 regs->reg_base.me_rnge.rme_srch_h = 7; in setup_vepu580_me()1918 regs->reg_base.me_rnge.rme_srch_v = 5; in setup_vepu580_me()1919 regs->reg_base.me_rnge.dlt_frm_num = 0; in setup_vepu580_me()
544 } me_rnge; member
506 } me_rnge; member
923 regs->me_rnge.cime_srch_v = 1; in setup_vepu541_intra_refresh()934 regs->me_rnge.cime_srch_h = 1; in setup_vepu541_intra_refresh()1306 regs->me_rnge.cime_srch_h = merangx / 32; in vepu541_h265_set_me_regs()1307 regs->me_rnge.cime_srch_v = merangy / 32; in vepu541_h265_set_me_regs()1309 regs->me_rnge.rime_srch_h = 7; in vepu541_h265_set_me_regs()1310 regs->me_rnge.rime_srch_v = 5; in vepu541_h265_set_me_regs()1311 regs->me_rnge.dlt_frm_num = 0x1; in vepu541_h265_set_me_regs()1337 RK_S32 swin_scope_wd16 = (regs->me_rnge.cime_srch_h + 3 + 1) / 4 * 2 + 1; in vepu541_h265_set_me_regs()1338 RK_S32 tmpMin = (regs->me_rnge.cime_srch_v + 3) / 4 * 2 + 1; in vepu541_h265_set_me_regs()1370 RK_S32 cime_srch_w = regs->me_rnge.cime_srch_h; in vepu540_h265_set_me_ram()
581 } me_rnge; member