Searched refs:max_supported_dppclk_khz (Results 1 – 7 of 7) sorted by relevance
46 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; in rv1_determine_dppclk_threshold()187 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; in ramp_up_dispclk_with_dpp()
1195 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()1199 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()1203 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()1207 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
391 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
358 int max_supported_dppclk_khz; member
3023 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in get_clock_requirements_for_state()
456 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz, in dcn10_log_hw_state()
3112 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel]…