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Searched refs:mali_hw_core_register_read (Results 1 – 11 of 11) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_pp.c145 …if (mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS) & MALI200_REG_VAL_STA… in mali_pp_stop_bus_wait()
150 … stop bus on %s. Status: 0x%08x\n", core->hw_core.description, mali_hw_core_register_read(&core->h… in mali_pp_stop_bus_wait()
224 if (reset_check_value == mali_hw_core_register_read(&core->hw_core, reset_wait_target_register)) { in mali_pp_hard_reset()
258 u32 status = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS); in mali_pp_reset_wait()
260 rawstat = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT); in mali_pp_reset_wait()
394 return mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_VERSION); in mali_pp_core_get_version()
425 irq_readout = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_STATUS); in mali_pp_irq_probe_ack()
439 …("Mali PP: Register MALI200_REG_ADDR_MGMT_VERSION = 0x%08X\n", mali_hw_core_register_read(&core->h…
440 …ster MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR = 0x%08X\n", mali_hw_core_register_read(&core->h…
441 … ("Mali PP: Register MALI200_REG_ADDR_MGMT_STATUS = 0x%08X\n", mali_hw_core_register_read(&core->h…
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H A Dmali_mmu.c168 …if (mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS) & MALI_MMU_STATUS_BIT_PAGI… in mali_mmu_enable_paging()
173 …ERROR(("Enable paging request failed, MMU status is 0x%08X\n", mali_hw_core_register_read(&mmu->hw… in mali_mmu_enable_paging()
185 u32 mmu_status = mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS); in mali_mmu_enable_stall()
200 mmu_status = mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS); in mali_mmu_enable_stall()
212 …INT(2, ("Enable stall request failed, MMU status is 0x%08X\n", mali_hw_core_register_read(&mmu->hw… in mali_mmu_enable_stall()
231 u32 mmu_status = mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS); in mali_mmu_disable_stall()
245 u32 status = mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS); in mali_mmu_disable_stall()
256 …NT(1, ("Disable stall request failed, MMU status is 0x%08X\n", mali_hw_core_register_read(&mmu->hw… in mali_mmu_disable_stall()
270 …MALI_DEBUG_ASSERT(0xCAFEB000 == mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_DTE_AD… in mali_mmu_raw_reset()
274 if (mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_DTE_ADDR) == 0) { in mali_mmu_raw_reset()
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H A Dmali_pmu.c97 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_up_all()
114 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_down_all()
129 MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_down()
137 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_down()
170 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_down()
189 MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_up()
197 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_up()
237 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_up()
255 rawstat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_wait_for_command_finish()
H A Dmali_mmu.h90 u32 rawstat_used = mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_INT_RAWSTAT); in mali_mmu_get_interrupt_result()
101 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_INT_STATUS); in mali_mmu_get_int_status()
106 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_INT_RAWSTAT); in mali_mmu_get_rawstat()
116 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS); in mali_mmu_get_status()
121 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_PAGE_FAULT_ADDR); in mali_mmu_get_page_fault_addr()
H A Dmali_gp.c105 …if (mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_STATUS) & MALIGP2_REG_VAL_STA… in mali_gp_stop_bus_wait()
134 if (reset_check_value == mali_hw_core_register_read(&core->hw_core, reset_wait_target_register)) { in mali_gp_hard_reset()
170 rawstat = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT); in mali_gp_reset_wait()
263 irq_readout = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT); in mali_gp_resume_with_new_heap()
285 return mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VERSION); in mali_gp_core_get_version()
308 irq_readout = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_STAT); in mali_gp_irq_probe_ack()
338 val0 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE); in mali_gp_update_performance_counters()
349 val1 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE); in mali_gp_update_performance_counters()
H A Dmali_gp.h63 u32 stat_used = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_STAT) & in mali_gp_get_interrupt_result()
85 return mali_hw_core_register_read(&core->hw_core, in mali_gp_get_rawstat()
91 u32 status = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_STATUS); in mali_gp_is_active()
124 return mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR); in mali_gp_read_plbu_alloc_start_addr()
H A Dmali_l2_cache.c136 cache_size = mali_hw_core_register_read(&cache->hw_core, in mali_l2_cache_create()
233 cache->counter_value0_base += mali_hw_core_register_read( in mali_l2_cache_power_down()
241 cache->counter_value1_base += mali_hw_core_register_read( in mali_l2_cache_power_down()
317 *value0 = mali_hw_core_register_read(&cache->hw_core, in mali_l2_cache_core_get_counter_values()
329 *value1 = mali_hw_core_register_read(&cache->hw_core, in mali_l2_cache_core_get_counter_values()
518 if (!(mali_hw_core_register_read(&cache->hw_core, in mali_l2_cache_send_command()
H A Dmali_pp.h89 u32 rawstat_used = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT) & in mali_pp_get_interrupt_result()
103 return mali_hw_core_register_read(&core->hw_core, in mali_pp_get_rawstat()
110 u32 status = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS); in mali_pp_is_active()
H A Dmali_group.c535 …MALI_PRINT(("0x%04x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i, mali_hw_core_register_read(&group->gp_core…
536 mali_hw_core_register_read(&group->gp_core->hw_core, i + 4),
537 mali_hw_core_register_read(&group->gp_core->hw_core, i + 8),
538 mali_hw_core_register_read(&group->gp_core->hw_core, i + 12)));
546 …MALI_PRINT(("0x%04x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i, mali_hw_core_register_read(&group->pp_core…
547 mali_hw_core_register_read(&group->pp_core->hw_core, i + 4),
548 mali_hw_core_register_read(&group->pp_core->hw_core, i + 8),
549 mali_hw_core_register_read(&group->pp_core->hw_core, i + 12)));
554 …MALI_PRINT(("0x%04x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i, mali_hw_core_register_read(&group->pp_core…
555 mali_hw_core_register_read(&group->pp_core->hw_core, i + 4),
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H A Dmali_pmu.h99 u32 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS); in mali_pmu_get_mask()
H A Dmali_hw_core.h47 MALI_STATIC_INLINE u32 mali_hw_core_register_read(struct mali_hw_core *core, u32 relative_address) in mali_hw_core_register_read() function