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Searched refs:kbase_reg_write (Results 1 – 25 of 34) sorted by relevance

12

/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/device/
H A Dmali_kbase_device_hw.c81 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), irq_bit); in busy_wait_on_irq()
99 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), FLUSH_PA_RANGE_COMPLETED); in kbase_gpu_cache_flush_pa_range_and_busy_wait()
105 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND_ARG0_LO), start_pa & U64_LO_MASK); in kbase_gpu_cache_flush_pa_range_and_busy_wait()
106 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND_ARG0_HI), in kbase_gpu_cache_flush_pa_range_and_busy_wait()
108 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND_ARG1_LO), end_pa & U64_LO_MASK); in kbase_gpu_cache_flush_pa_range_and_busy_wait()
109 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND_ARG1_HI), (end_pa & U64_HI_MASK) >> 32); in kbase_gpu_cache_flush_pa_range_and_busy_wait()
110 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), flush_op); in kbase_gpu_cache_flush_pa_range_and_busy_wait()
142 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_cache_flush_and_busy_wait()
158 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), in kbase_gpu_cache_flush_and_busy_wait()
164 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), flush_op); in kbase_gpu_cache_flush_and_busy_wait()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_instr_backend.c50 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbasep_instr_hwcnt_cacheclean()
57 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), in kbasep_instr_hwcnt_cacheclean()
101 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | in kbase_instr_hwcnt_enable_internal()
144 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), in kbase_instr_hwcnt_enable_internal()
147 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO), in kbase_instr_hwcnt_enable_internal()
149 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI), in kbase_instr_hwcnt_enable_internal()
151 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN), in kbase_instr_hwcnt_enable_internal()
153 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_EN), in kbase_instr_hwcnt_enable_internal()
155 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_MMU_L2_EN), in kbase_instr_hwcnt_enable_internal()
160 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_TILER_EN), 0, in kbase_instr_hwcnt_enable_internal()
[all …]
H A Dmali_kbase_mmu_hw_direct.c96 kbase_reg_write(kbdev, MMU_AS_REG(as_nr, AS_COMMAND), cmd, in write_cmd()
147 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_mmu_interrupt()
247 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask, NULL); in kbase_mmu_interrupt()
274 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSCFG_LO), in kbase_mmu_hw_configure()
276 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSCFG_HI), in kbase_mmu_hw_configure()
284 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSTAB_LO), in kbase_mmu_hw_configure()
286 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSTAB_HI), in kbase_mmu_hw_configure()
289 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_MEMATTR_LO), in kbase_mmu_hw_configure()
291 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_MEMATTR_HI), in kbase_mmu_hw_configure()
317 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_LOCKADDR_LO), in kbase_mmu_hw_do_operation()
[all …]
H A Dmali_kbase_pm_driver.c154 kbase_reg_write(kbdev, in mali_cci_flush_l2()
278 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg), lo, NULL); in kbase_pm_invoke()
281 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg + 4), hi, NULL); in kbase_pm_invoke()
1012 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), GPU_IRQ_REG_ALL, in kbase_pm_enable_interrupts()
1014 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), GPU_IRQ_REG_ALL, in kbase_pm_enable_interrupts()
1018 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_CLEAR), 0xFFFFFFFF, in kbase_pm_enable_interrupts()
1020 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1022 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1023 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1037 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
[all …]
H A Dmali_kbase_irq_linux.c249 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_CLEAR), val, NULL); in kbase_job_irq_test_handler()
281 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val, NULL); in kbase_mmu_irq_test_handler()
327 kbase_reg_write(kbdev, mask_offset, 0x0, NULL); in kbasep_common_test_interrupt()
341 kbase_reg_write(kbdev, mask_offset, 0x1, NULL); in kbasep_common_test_interrupt()
342 kbase_reg_write(kbdev, rawstat_offset, 0x1, NULL); in kbasep_common_test_interrupt()
364 kbase_reg_write(kbdev, mask_offset, 0x0, NULL); in kbasep_common_test_interrupt()
380 kbase_reg_write(kbdev, mask_offset, old_mask_val, NULL); in kbasep_common_test_interrupt()
H A Dmali_kbase_device_hw.c152 void kbase_reg_write(struct kbase_device *kbdev, u16 offset, u32 value, in kbase_reg_write() function
173 KBASE_EXPORT_TEST_API(kbase_reg_write);
244 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val, NULL); in kbase_gpu_interrupt()
H A Dmali_kbase_jm_hw.c73 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_HEAD_NEXT_LO), in kbase_job_hw_submit()
75 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_HEAD_NEXT_HI), in kbase_job_hw_submit()
78 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_AFFINITY_NEXT_LO), in kbase_job_hw_submit()
80 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_AFFINITY_NEXT_HI), in kbase_job_hw_submit()
125 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_CONFIG_NEXT), cfg, kctx); in kbase_job_hw_submit()
128 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_FLUSH_ID_NEXT), in kbase_job_hw_submit()
174 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_COMMAND_NEXT), in kbase_job_hw_submit()
315 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_CLEAR), in kbase_job_done()
606 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_COMMAND), action, kctx); in kbasep_job_slot_soft_or_hard_stop_do_action()
H A Dmali_kbase_cache_policy_backend.c27 kbase_reg_write(kbdev, COHERENCY_ENABLE, mode, NULL); in kbase_cache_set_coherency_mode()
H A Dmali_kbase_device_internal.h38 void kbase_reg_write(struct kbase_device *kbdev, u16 offset, u32 value,
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_dummy_job_wa.c119 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_HEAD_NEXT_LO), in run_job()
121 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_HEAD_NEXT_HI), in run_job()
123 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_AFFINITY_NEXT_LO), in run_job()
125 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_AFFINITY_NEXT_HI), in run_job()
127 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_CONFIG_NEXT), in run_job()
131 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_COMMAND_NEXT), in run_job()
137 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_CLEAR), done); in run_job()
177 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), 0); in kbase_dummy_job_wa_execute()
178 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK), 0); in kbase_dummy_job_wa_execute()
181 kbase_reg_write(kbdev, SHADER_PWRON_LO, (cores & U32_MAX)); in kbase_dummy_job_wa_execute()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_instr_backend.c78 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | in kbase_instr_hwcnt_enable_internal()
103 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), in kbase_instr_hwcnt_enable_internal()
111 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO), in kbase_instr_hwcnt_enable_internal()
113 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI), in kbase_instr_hwcnt_enable_internal()
116 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN), in kbase_instr_hwcnt_enable_internal()
119 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_EN), in kbase_instr_hwcnt_enable_internal()
121 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_MMU_L2_EN), in kbase_instr_hwcnt_enable_internal()
124 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_TILER_EN), in kbase_instr_hwcnt_enable_internal()
127 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), in kbase_instr_hwcnt_enable_internal()
156 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~PRFCNT_SAMPLE_COMPLETED); in kbasep_instr_hwc_disable_hw_prfcnt()
[all …]
H A Dmali_kbase_cache_policy_backend.c49 kbase_reg_write(kbdev, AMBA_ENABLE, val); in kbase_cache_set_coherency_mode()
51 kbase_reg_write(kbdev, COHERENCY_ENABLE, mode); in kbase_cache_set_coherency_mode()
75 kbase_reg_write(kbdev, AMBA_ENABLE, val); in kbase_amba_set_memory_cache_support()
88 kbase_reg_write(kbdev, AMBA_ENABLE, val); in kbase_amba_set_invalidate_hint()
H A Dmali_kbase_pm_driver.c281 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), in mali_cci_flush_l2()
376 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg), lo); in kbase_pm_invoke()
378 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg + 4), hi); in kbase_pm_invoke()
544 kbase_reg_write(kbdev, GPU_CONTROL_REG(L2_CONFIG), in kbase_pm_l2_config_override()
578 kbase_reg_write(kbdev, GPU_CONTROL_REG(ASN_HASH(i)), in kbase_pm_l2_config_override()
584 kbase_reg_write(kbdev, GPU_CONTROL_REG(L2_CONFIG), val); in kbase_pm_l2_config_override()
679 kbase_reg_write(kbdev, GPU_CONTROL_REG(MCU_CONTROL), val); in kbase_pm_enable_mcu_db_notification()
737 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), POWER_CHANGED_ALL); in kbasep_pm_toggle_power_interrupt()
742 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask); in kbasep_pm_toggle_power_interrupt()
2530 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), GPU_IRQ_REG_ALL);
[all …]
H A Dmali_kbase_irq_linux.c282 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_CLEAR), val); in kbase_job_irq_test_handler()
313 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val); in kbase_mmu_irq_test_handler()
359 kbase_reg_write(kbdev, mask_offset, 0x0); in kbasep_common_test_interrupt()
373 kbase_reg_write(kbdev, mask_offset, 0x1); in kbasep_common_test_interrupt()
374 kbase_reg_write(kbdev, rawstat_offset, 0x1); in kbasep_common_test_interrupt()
396 kbase_reg_write(kbdev, mask_offset, 0x0); in kbasep_common_test_interrupt()
412 kbase_reg_write(kbdev, mask_offset, old_mask_val); in kbasep_common_test_interrupt()
H A Dmali_kbase_jm_hw.c108 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_AFFINITY_NEXT_LO), in kbase_job_write_affinity()
110 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_AFFINITY_NEXT_HI), in kbase_job_write_affinity()
233 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_HEAD_NEXT_LO), in kbase_job_hw_submit()
235 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_HEAD_NEXT_HI), in kbase_job_hw_submit()
292 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_CONFIG_NEXT), cfg); in kbase_job_hw_submit()
295 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_FLUSH_ID_NEXT), in kbase_job_hw_submit()
347 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_COMMAND_NEXT), in kbase_job_hw_submit()
502 kbase_reg_write(kbdev, JOB_CONTROL_REG(JOB_IRQ_CLEAR), in kbase_job_done()
675 kbase_reg_write(kbdev, JOB_SLOT_REG(js, JS_COMMAND), action); in kbasep_job_slot_soft_or_hard_stop_do_action()
H A Dmali_kbase_model_linux.c145 void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value) in kbase_reg_write() function
154 KBASE_EXPORT_TEST_API(kbase_reg_write);
H A Dmali_kbase_pm_internal.h969 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_pm_enable_db_mirror_interrupt()
991 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_pm_disable_db_mirror_interrupt()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/csf/ipa_control/
H A Dmali_kbase_csf_ipa_control.c119 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_CSHW_LO), select_cshw_lo); in apply_select_config()
120 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_CSHW_HI), select_cshw_hi); in apply_select_config()
121 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_MEMSYS_LO), in apply_select_config()
123 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_MEMSYS_HI), in apply_select_config()
125 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_TILER_LO), in apply_select_config()
127 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_TILER_HI), in apply_select_config()
129 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_SHADER_LO), in apply_select_config()
131 kbase_reg_write(kbdev, IPA_CONTROL_REG(SELECT_SHADER_HI), in apply_select_config()
137 kbase_reg_write(kbdev, IPA_CONTROL_REG(COMMAND), COMMAND_APPLY); in apply_select_config()
318 kbase_reg_write(kbdev, IPA_CONTROL_REG(TIMER), in kbase_ipa_control_rate_change_notify()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_hw_direct.c208 kbase_reg_write(kbdev, MMU_AS_REG(as_nr, AS_COMMAND), cmd); in write_cmd()
342 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSCFG_LO), in kbase_mmu_hw_configure()
344 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSCFG_HI), in kbase_mmu_hw_configure()
347 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSTAB_LO), in kbase_mmu_hw_configure()
349 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_TRANSTAB_HI), in kbase_mmu_hw_configure()
352 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_MEMATTR_LO), in kbase_mmu_hw_configure()
354 kbase_reg_write(kbdev, MMU_AS_REG(as->number, AS_MEMATTR_HI), in kbase_mmu_hw_configure()
402 kbase_reg_write(kbdev, MMU_AS_REG(as_nr, AS_LOCKADDR_LO), in mmu_hw_set_lock_addr()
404 kbase_reg_write(kbdev, MMU_AS_REG(as_nr, AS_LOCKADDR_HI), in mmu_hw_set_lock_addr()
663 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask); in kbase_mmu_hw_clear_fault()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/device/backend/
H A Dmali_kbase_device_hw_csf.c103 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_interrupt()
145 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val & ~CLEAN_CACHES_COMPLETED); in kbase_gpu_interrupt()
205 void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value) in kbase_reg_write() function
225 KBASE_EXPORT_TEST_API(kbase_reg_write);
H A Dmali_kbase_device_hw_jm.c71 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val & ~CLEAN_CACHES_COMPLETED); in kbase_gpu_interrupt()
110 void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value) in kbase_reg_write() function
123 KBASE_EXPORT_TEST_API(kbase_reg_write);
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/mmu/backend/
H A Dmali_kbase_mmu_csf.c190 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), in kbase_gpu_report_bus_fault_and_kill()
298 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), in kbase_mmu_interrupt_process()
373 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
437 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
496 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), in kbase_mmu_gpu_fault_worker()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/midgard/tests/mali_kutf_irq_test/
H A Dmali_kutf_irq_test_main.c95 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val, in kbase_gpu_irq_custom_handler()
191 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), in mali_kutf_irq_latency()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/tests/mali_kutf_irq_test/
H A Dmali_kutf_irq_test_main.c99 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), in kbase_gpu_irq_custom_handler()
197 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), in mali_kutf_irq_latency()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/platform/meson/
H A Dmali_kbase_runtime_pm.c92 kbase_reg_write(kbdev, GPU_CONTROL_REG(PWR_KEY), 0x2968A819); in pm_callback_soft_reset()
93 kbase_reg_write(kbdev, GPU_CONTROL_REG(PWR_OVERRIDE1), in pm_callback_soft_reset()

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