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Searched refs:ixCG_SPLL_FUNC_CNTL (Results 1 – 11 of 11) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c62 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
83 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
H A Dci_baco.c64 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
94 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
H A Dpolaris_baco.c61 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
153 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
H A Dtonga_baco.c62 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
85 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
H A Dsmu7_hwmgr.c4388 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); in smu7_read_clock_registers()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
H A Dsmu_7_1_1_d.h45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
H A Dsmu_7_1_2_d.h45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
H A Dsmu_7_0_1_d.h45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
H A Dsmu_7_1_3_d.h48 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro
H A Dsmu_7_1_0_d.h45 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 macro