Searched refs:dsiclk_sel (Results 1 – 1 of 1) sorted by relevance
47 u32 dsiclk_sel; /* Mux configuration (see diagram) */ member218 pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ in dsi_pll_14nm_input_init()523 data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */ in pll_db_commit_14nm()