| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
[all …]
|
| H A D | dcn20_dccg.h | 116 struct dccg base;
122 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
124 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
128 void dccg2_init(struct dccg *dccg);
130 struct dccg *dccg2_create(
136 void dcn_dccg_destroy(struct dccg **dccg);
|
| H A D | dcn20_hwseq.c | 2429 if (res_pool->dccg->funcs->dccg_init) in dcn20_fpga_init_hw()
2430 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn20_fpga_init_hw()
|
| H A D | dcn20_resource.c | 1560 if (pool->base.dccg != NULL) in dcn20_resource_destruct()
1561 dcn_dccg_destroy(&pool->base.dccg); in dcn20_resource_destruct()
3914 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3915 if (pool->base.dccg == NULL) {
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 32 struct dccg { struct
40 void (*update_dpp_dto)(struct dccg *dccg, argument
43 void (*get_dccg_ref_freq)(struct dccg *dccg,
46 void (*dccg_init)(struct dccg *dccg);
|
| H A D | clk_mgr.h | 281 struct dccg;
283 …clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
|
| H A D | clk_mgr_internal.h | 223 struct dccg *dccg; member
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
52 struct dccg *dccg3_create( in dccg3_create()
59 struct dccg *base; in dccg3_create()
77 struct dccg *dccg30_create( in dccg30_create()
84 struct dccg *base; in dccg30_create()
|
| H A D | dcn30_dccg.h | 54 struct dccg *dccg3_create(
60 struct dccg *dccg30_create(
|
| H A D | dcn30_hwseq.c | 445 if (res_pool->dccg->funcs->dccg_init) in dcn30_init_hw()
446 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn30_init_hw()
480 if (res_pool->dccg && res_pool->hubbub) { in dcn30_init_hw()
482 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn30_init_hw()
|
| H A D | dcn30_resource.c | 1322 if (pool->base.dccg != NULL) in dcn30_resource_destruct()
1323 dcn_dccg_destroy(&pool->base.dccg); in dcn30_resource_destruct()
2718 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn30_resource_construct()
2719 if (pool->base.dccg == NULL) { in dcn30_resource_construct()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 115 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
166 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
171 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
188 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
192 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
|
| H A D | dcn20_clk_mgr.c | 108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
118 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
121 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
326 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
461 struct dccg *dccg) in dcn20_clk_mgr_construct() argument
470 clk_mgr->dccg = dccg; in dcn20_clk_mgr_construct()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.h | 39 struct dccg *dccg);
|
| H A D | rn_clk_mgr.c | 845 struct dccg *dccg) in rn_clk_mgr_construct() argument
861 clk_mgr->dccg = dccg; in rn_clk_mgr_construct()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.h | 34 struct dccg *dccg);
|
| H A D | dcn30_clk_mgr.c | 505 struct dccg *dccg) in dcn3_clk_mgr_construct() argument
513 clk_mgr->dccg = dccg; in dcn3_clk_mgr_construct()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.h | 48 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 237 struct dccg *dccg; member
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 1276 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init) in dcn10_init_hw()
1277 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn10_init_hw()
1311 if (res_pool->dccg && res_pool->hubbub) { in dcn10_init_hw()
1313 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn10_init_hw()
2525 if (dc->res_pool->dccg) in dcn10_update_dchubp_dpp()
2526 dc->res_pool->dccg->funcs->update_dpp_dto( in dcn10_update_dchubp_dpp()
2527 dc->res_pool->dccg, in dcn10_update_dchubp_dpp()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_hw_sequencer.c | 2514 struct clk_mgr *dccg = dc->clk_mgr; in dce110_prepare_bandwidth() local
2518 dccg->funcs->update_clocks( in dce110_prepare_bandwidth()
2519 dccg, in dce110_prepare_bandwidth()
2528 struct clk_mgr *dccg = dc->clk_mgr; in dce110_optimize_bandwidth() local
2532 dccg->funcs->update_clocks( in dce110_optimize_bandwidth()
2533 dccg, in dce110_optimize_bandwidth()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 1017 if (pool->base.dccg != NULL) in dcn21_resource_destruct()
1018 dcn_dccg_destroy(&pool->base.dccg); in dcn21_resource_destruct()
1923 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn21_resource_construct()
1924 if (pool->base.dccg == NULL) { in dcn21_resource_construct()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 731 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
|