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Searched refs:cw0 (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/board/freescale/common/
H A Dics307_clk.c101 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) in ics307_clk_freq() argument
106 unsigned long od = ics307_s_to_od[cw0 & 0x7]; in ics307_clk_freq()
127 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, in ics307_clk_freq()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c84 const struct dmub_window *cw0, in dmub_dcn30_backdoor_load() argument
96 dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
100 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn30_backdoor_load()
102 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn30_backdoor_load()
H A Ddmub_dcn20.c143 const struct dmub_window *cw0, in dmub_dcn20_backdoor_load() argument
155 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn20_backdoor_load()
159 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn20_backdoor_load()
161 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn20_backdoor_load()
H A Ddmub_srv.c388 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
399 cw0.offset.quad_part = inst_fb->gpu_addr; in dmub_srv_hw_init()
400 cw0.region.base = DMUB_CW0_BASE; in dmub_srv_hw_init()
401 cw0.region.top = cw0.region.base + inst_fb->size - 1; in dmub_srv_hw_init()
415 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); in dmub_srv_hw_init()
H A Ddmub_dcn30.h38 const struct dmub_window *cw0,
H A Ddmub_dcn20.h166 const struct dmub_window *cw0,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h242 const struct dmub_window *cw0,