1 /* 2 * drivers/media/platform/sunxi-vin/vin_test/sunxi_camera_v2.h -- Ctrl IDs definitions for sunxi-vin 3 * 4 * Copyright (C) 2014 Allwinnertech Co., Ltd. 5 * Copyright (C) 2015 Yang Feng 6 * 7 * Author: Yang Feng <yangfeng@allwinnertech.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 #ifndef _SUNXI_CAMERA_H_ 20 #define _SUNXI_CAMERA_H_ 21 22 #include <linux/types.h> 23 #include <linux/videodev2.h> 24 25 /* Flags for 'capability' and 'capturemode' fields */ 26 #define V4L2_MODE_HIGHQUALITY 0x0001 27 #define V4L2_MODE_VIDEO 0x0002 28 #define V4L2_MODE_IMAGE 0x0003 29 #define V4L2_MODE_PREVIEW 0x0004 30 31 /* for yuv420 FBC mode*/ 32 #define V4L2_PIX_FMT_FBC v4l2_fourcc('F', 'C', '2', '1') 33 #define V4L2_PIX_FMT_LBC_2_0X v4l2_fourcc('L', 'C', '2', '1') 34 #define V4L2_PIX_FMT_LBC_2_5X v4l2_fourcc('L', 'C', '2', '2') 35 #define V4L2_PIX_FMT_LBC_1_0X v4l2_fourcc('L', 'C', '2', '3') 36 37 /* 38 * USER CIDS 39 */ 40 struct v4l2_win_coordinate { 41 __s32 x1; 42 __s32 y1; 43 __s32 x2; 44 __s32 y2; 45 }; 46 47 /* 48 *enum v4l2_flash_led_mode { 49 * V4L2_FLASH_LED_MODE_NONE, 50 * V4L2_FLASH_LED_MODE_FLASH, 51 * V4L2_FLASH_LED_MODE_TORCH, 52 *}; 53 */ 54 #define V4L2_FLASH_LED_MODE_AUTO (V4L2_FLASH_LED_MODE_TORCH + 1) 55 #define V4L2_FLASH_LED_MODE_RED_EYE (V4L2_FLASH_LED_MODE_TORCH + 2) 56 57 struct v4l2_win_setting { 58 struct v4l2_win_coordinate coor; 59 }; 60 61 enum v4l2_gain_shift { 62 V4L2_GAIN_SHIFT = 0, 63 V4L2_SHARP_LEVEL_SHIFT = 8, 64 V4L2_SHARP_MIN_SHIFT = 20, 65 V4L2_NDF_SHIFT = 26, 66 }; 67 68 #define MAX_EXP_FRAMES 5 69 70 /* 71 * The base for the sunxi-vfe controls. 72 * Total of 64 controls is reserved for this driver, add by yangfeng 73 */ 74 #define V4L2_CID_USER_SUNXI_CAMERA_BASE (V4L2_CID_USER_BASE + 0x1050) 75 76 #define V4L2_CID_AUTO_FOCUS_INIT (V4L2_CID_USER_SUNXI_CAMERA_BASE + 2) 77 #define V4L2_CID_AUTO_FOCUS_RELEASE (V4L2_CID_USER_SUNXI_CAMERA_BASE + 3) 78 #define V4L2_CID_GSENSOR_ROTATION (V4L2_CID_USER_SUNXI_CAMERA_BASE + 4) 79 #define V4L2_CID_FRAME_RATE (V4L2_CID_USER_SUNXI_CAMERA_BASE + 5) 80 81 enum v4l2_take_picture { 82 V4L2_TAKE_PICTURE_STOP = 0, 83 V4L2_TAKE_PICTURE_NORM = 1, 84 V4L2_TAKE_PICTURE_FAST = 2, 85 V4L2_TAKE_PICTURE_FLASH = 3, 86 V4L2_TAKE_PICTURE_HDR = 4, 87 }; 88 struct isp_hdr_setting_t { 89 __s32 hdr_en; 90 __s32 hdr_mode; 91 __s32 frames_count; 92 __s32 total_frames; 93 __s32 values[MAX_EXP_FRAMES]; 94 }; 95 struct csi_sync_ctrl { 96 __s32 type; 97 __s32 prs_sync_en; 98 __s32 prs_sync_scr_sel; 99 __s32 prs_sync_bench_sel; 100 __s32 prs_sync_input_vsync_en; 101 __s32 prs_sync_singal_via_by; 102 __s32 prs_sync_singal_scr_sel; 103 __s32 prs_sync_pulse_cfg; 104 __s32 prs_sync_dist; 105 __s32 prs_sync_wait_n; 106 __s32 prs_sync_wait_m; 107 __s32 dma_clr_dist; 108 109 __s32 prs_xvs_out_en; 110 __s32 prs_xhs_out_en; 111 __s32 prs_xvs_t; 112 __s32 prs_xhs_t; 113 __s32 prs_xvs_len; 114 __s32 prs_xhs_len; 115 }; 116 117 #define HDR_CTRL_GET 0 118 #define HDR_CTRL_SET 1 119 struct isp_hdr_ctrl { 120 __s32 flag; 121 __s32 count; 122 struct isp_hdr_setting_t hdr_t; 123 }; 124 125 #define V4L2_CID_TAKE_PICTURE (V4L2_CID_USER_SUNXI_CAMERA_BASE + 6) 126 127 typedef union { 128 unsigned int dwval; 129 struct { 130 unsigned int af_sharp:16; 131 unsigned int hdr_cnt:4; 132 unsigned int flash_ok:1; 133 unsigned int capture_ok:1; 134 unsigned int fast_capture_ok:1; 135 unsigned int res0:9; 136 } bits; 137 } IMAGE_FLAG_t; 138 139 #define V4L2_CID_HOR_VISUAL_ANGLE (V4L2_CID_USER_SUNXI_CAMERA_BASE + 7) 140 #define V4L2_CID_VER_VISUAL_ANGLE (V4L2_CID_USER_SUNXI_CAMERA_BASE + 8) 141 #define V4L2_CID_FOCUS_LENGTH (V4L2_CID_USER_SUNXI_CAMERA_BASE + 9) 142 #define V4L2_CID_R_GAIN (V4L2_CID_USER_SUNXI_CAMERA_BASE + 10) 143 #define V4L2_CID_GR_GAIN (V4L2_CID_USER_SUNXI_CAMERA_BASE + 11) 144 #define V4L2_CID_GB_GAIN (V4L2_CID_USER_SUNXI_CAMERA_BASE + 12) 145 #define V4L2_CID_B_GAIN (V4L2_CID_USER_SUNXI_CAMERA_BASE + 13) 146 147 enum v4l2_sensor_type { 148 V4L2_SENSOR_TYPE_YUV = 0, 149 V4L2_SENSOR_TYPE_RAW = 1, 150 }; 151 152 #define V4L2_CID_SENSOR_TYPE (V4L2_CID_USER_SUNXI_CAMERA_BASE + 14) 153 154 #define V4L2_CID_AE_WIN_X1 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 15) 155 #define V4L2_CID_AE_WIN_Y1 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 16) 156 #define V4L2_CID_AE_WIN_X2 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 17) 157 #define V4L2_CID_AE_WIN_Y2 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 18) 158 159 #define V4L2_CID_AF_WIN_X1 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 19) 160 #define V4L2_CID_AF_WIN_Y1 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 20) 161 #define V4L2_CID_AF_WIN_X2 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 21) 162 #define V4L2_CID_AF_WIN_Y2 (V4L2_CID_USER_SUNXI_CAMERA_BASE + 22) 163 164 /* 165 * PRIVATE IOCTRLS 166 */ 167 168 struct isp_stat_buf { 169 void *buf; 170 __u32 buf_size; 171 }; 172 struct isp_exif_attribute { 173 struct v4l2_fract exposure_time; 174 struct v4l2_fract shutter_speed; 175 __u32 fnumber; 176 __u32 focal_length; 177 __s32 exposure_bias; 178 __u32 iso_speed; 179 __u32 flash_fire; 180 __u32 brightness; 181 __s32 reserved[16]; 182 }; 183 184 struct vin_top_clk { 185 __u32 clk_rate; 186 }; 187 188 struct vin_fps_ds { 189 __u32 fps_ds; 190 }; 191 192 struct isp_debug_mode { 193 __u32 debug_en; 194 __u32 debug_sel; 195 }; 196 197 struct vin_pattern_config { 198 __u32 ptn_en; 199 void *ptn_addr; 200 void *drc_tab; 201 void *gamma_tab; 202 void *isp_reg; 203 __u32 ptn_size; 204 __u32 ptn_w; 205 __u32 ptn_h; 206 __u32 ptn_fmt; 207 __u32 ptn_type; 208 }; 209 210 struct vin_reset_time { 211 __u32 reset_time; 212 }; 213 214 struct parser_fps_ds { 215 __u32 ch0_fps_ds; 216 __u32 ch1_fps_ds; 217 __u32 ch2_fps_ds; 218 __u32 ch3_fps_ds; 219 }; 220 221 #define VIDIOC_ISP_AE_STAT_REQ \ 222 _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct isp_stat_buf) 223 #define VIDIOC_ISP_HIST_STAT_REQ \ 224 _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct isp_stat_buf) 225 #define VIDIOC_ISP_AF_STAT_REQ \ 226 _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct isp_stat_buf) 227 #define VIDIOC_ISP_EXIF_REQ \ 228 _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct isp_exif_attribute) 229 #define VIDIOC_ISP_GAMMA_REQ \ 230 _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct isp_stat_buf) 231 #define VIDIOC_SET_TOP_CLK \ 232 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct vin_top_clk) 233 #define VIDIOC_SET_FPS_DS \ 234 _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct vin_fps_ds) 235 #define VIDIOC_HDR_CTRL \ 236 _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct isp_hdr_ctrl) 237 #define VIDIOC_SYNC_CTRL \ 238 _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct csi_sync_ctrl) 239 #define VIDIOC_ISP_DEBUG \ 240 _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct isp_debug_mode) 241 #define VIDIOC_VIN_PTN_CFG \ 242 _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct vin_pattern_config) 243 #define VIDIOC_VIN_RESET_TIME \ 244 _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct vin_reset_time) 245 #define VIDIOC_SET_PARSER_FPS \ 246 _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct parser_fps_ds) 247 248 249 /* 250 * Events 251 * 252 * V4L2_EVENT_VIN_H3A: Histogram and AWB AE AF statistics data ready 253 * V4L2_EVENT_VIN_ISP_OFF: ISP stream off 254 */ 255 256 #define V4L2_EVENT_VIN_CLASS (V4L2_EVENT_PRIVATE_START | 0x100) 257 #define V4L2_EVENT_VIN_H3A (V4L2_EVENT_VIN_CLASS | 0x1) 258 #define V4L2_EVENT_VIN_HDR (V4L2_EVENT_VIN_CLASS | 0x2) 259 #define V4L2_EVENT_VIN_ISP_OFF (V4L2_EVENT_VIN_CLASS | 0x3) 260 261 struct vin_isp_h3a_config { 262 __u32 buf_size; 263 __u32 config_counter; 264 }; 265 266 /** 267 * struct vin_isp_stat_data - Statistic data sent to or received from user 268 * @ts: Timestamp of returned framestats. 269 * @buf: Pointer to pass to user. 270 * @frame_number: Frame number of requested stats. 271 * @cur_frame: Current frame number being processed. 272 * @config_counter: Number of the configuration associated with the data. 273 */ 274 struct vin_isp_stat_data { 275 void *buf; 276 __u32 buf_size; 277 __u32 frame_number; 278 __u32 config_counter; 279 }; 280 281 struct vin_isp_stat_event_status { 282 __u32 frame_number; 283 __u16 config_counter; 284 __u8 buf_err; 285 }; 286 287 struct vin_isp_hdr_event_data { 288 __u32 cmd; 289 struct isp_hdr_ctrl hdr; 290 }; 291 292 struct vin_vsync_event_data { 293 __u64 frame_number; 294 }; 295 296 /* 297 * Statistics IOCTLs 298 * 299 * VIDIOC_VIN_ISP_H3A_CFG: Set AE configuration 300 * VIDIOC_VIN_ISP_STAT_REQ: Read statistics (AE/AWB/AF/histogram) data 301 * VIDIOC_VIN_ISP_STAT_EN: Enable/disable a statistics module 302 */ 303 304 #define VIDIOC_VIN_ISP_H3A_CFG \ 305 _IOWR('V', BASE_VIDIOC_PRIVATE + 31, struct vin_isp_h3a_config) 306 #define VIDIOC_VIN_ISP_STAT_REQ \ 307 _IOWR('V', BASE_VIDIOC_PRIVATE + 32, struct vin_isp_stat_data) 308 #define VIDIOC_VIN_ISP_STAT_EN \ 309 _IOWR('V', BASE_VIDIOC_PRIVATE + 33, unsigned int) 310 311 struct sensor_config { 312 int width; 313 int height; 314 unsigned int hoffset; /*receive hoffset from sensor output*/ 315 unsigned int voffset; /*receive voffset from sensor output*/ 316 unsigned int hts; /*h size of timing, unit: pclk */ 317 unsigned int vts; /*v size of timing, unit: line */ 318 unsigned int pclk; /*pixel clock in Hz */ 319 unsigned int fps_fixed; /*sensor fps */ 320 unsigned int bin_factor;/*binning factor */ 321 unsigned int intg_min; /*integration min, unit: line, Q4 */ 322 unsigned int intg_max; /*integration max, unit: line, Q4 */ 323 unsigned int gain_min; /*sensor gain min, Q4 */ 324 unsigned int gain_max; /*sensor gain max, Q4 */ 325 unsigned int mbus_code; /*media bus code */ 326 unsigned int wdr_mode; /*isp wdr mode */ 327 }; 328 329 struct sensor_exp_gain { 330 int exp_val; 331 int gain_val; 332 int r_gain; 333 int b_gain; 334 }; 335 336 struct sensor_fps { 337 int fps; 338 }; 339 struct sensor_temp { 340 int temp; 341 }; 342 343 struct isp_table_reg_map { 344 void *addr; 345 unsigned int size; 346 }; 347 348 struct actuator_ctrl { 349 unsigned int code; 350 }; 351 352 struct actuator_para { 353 unsigned short code_min; 354 unsigned short code_max; 355 }; 356 357 /* 358 * Camera Sensor IOCTLs 359 */ 360 361 #define VIDIOC_VIN_SENSOR_CFG_REQ \ 362 _IOWR('V', BASE_VIDIOC_PRIVATE + 60, struct sensor_config) 363 364 #define VIDIOC_VIN_SENSOR_EXP_GAIN \ 365 _IOWR('V', BASE_VIDIOC_PRIVATE + 61, struct sensor_exp_gain) 366 #define VIDIOC_VIN_SENSOR_SET_FPS \ 367 _IOWR('V', BASE_VIDIOC_PRIVATE + 62, struct sensor_fps) 368 #define VIDIOC_VIN_SENSOR_GET_TEMP \ 369 _IOWR('V', BASE_VIDIOC_PRIVATE + 63, struct sensor_temp) 370 371 #define VIDIOC_VIN_ACT_SET_CODE \ 372 _IOWR('V', BASE_VIDIOC_PRIVATE + 64, struct actuator_ctrl) 373 #define VIDIOC_VIN_ACT_INIT \ 374 _IOWR('V', BASE_VIDIOC_PRIVATE + 65, struct actuator_para) 375 376 #define VIDIOC_VIN_ISP_LOAD_REG \ 377 _IOWR('V', BASE_VIDIOC_PRIVATE + 70, struct isp_table_reg_map) 378 379 #define VIDIOC_VIN_ISP_TABLE1_MAP \ 380 _IOWR('V', BASE_VIDIOC_PRIVATE + 71, struct isp_table_reg_map) 381 382 #define VIDIOC_VIN_ISP_TABLE2_MAP \ 383 _IOWR('V', BASE_VIDIOC_PRIVATE + 72, struct isp_table_reg_map) 384 385 #define VIDIOC_VIN_GET_SENSOR_CODE \ 386 _IOWR('V', BASE_VIDIOC_PRIVATE + 73, int) 387 388 #endif /*_SUNXI_CAMERA_H_*/ 389 390