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Searched refs:cfgcr1 (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c1132 i915_reg_t ctl, cfgcr1, cfgcr2; member
1145 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1151 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1157 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1187 intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1189 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1249 hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1544 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1560 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | in skl_ddi_hdmi_pll_dividers()
1574 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_hdmi_pll_dividers()
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H A Dintel_dpll_mgr.h188 u32 cfgcr1, cfgcr2; member
H A Dintel_display_debugfs.c943 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); in i915_shared_dplls_info()
H A Dintel_display.c13995 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()