| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/ |
| H A D | halbb_init.c | 17 bool halbb_chk_bb_rf_pkg_set_valid(struct bb_info *bb) in halbb_chk_bb_rf_pkg_set_valid() argument
19 struct rtw_hal_com_t *hal_i = bb->hal_com; in halbb_chk_bb_rf_pkg_set_valid()
24 switch (bb->ic_type) { in halbb_chk_bb_rf_pkg_set_valid()
27 valid = halbb_chk_pkg_valid_8852a(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
33 valid = halbb_chk_pkg_valid_8852a_2(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
39 valid = halbb_chk_pkg_valid_8852b(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
45 valid = halbb_chk_pkg_valid_8852c(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
51 valid = halbb_chk_pkg_valid_8834a(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
63 void halbb_ic_hw_setting_init(struct bb_info *bb) in halbb_ic_hw_setting_init() argument
66 halbb_tdma_cr_sel_init(bb); in halbb_ic_hw_setting_init()
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| H A D | halbb_fwofld.c | 28 bool halbb_check_fw_ofld(struct bb_info *bb) in halbb_check_fw_ofld() argument
30 bool ret = bb->phl_com->dev_cap.fw_cap.offload_cap & BIT0; in halbb_check_fw_ofld()
32 BB_DBG(bb, DBG_FW_INFO, "FW ofld ret = %d\n", (u8)ret); in halbb_check_fw_ofld()
36 bool halbb_fw_delay(struct bb_info *bb, u32 val) in halbb_fw_delay() argument
45 ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd); in halbb_fw_delay()
46 BB_DBG(bb, DBG_FW_INFO, "FW ofld delay:%x\n", val); in halbb_fw_delay()
56 bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc) in halbb_fw_set_reg() argument
68 ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd); in halbb_fw_set_reg()
69 BB_DBG(bb, DBG_FW_INFO, "FW ofld addr:%x, val:%x, msk:%x\n", addr, val, mask); in halbb_fw_set_reg()
80 bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, in halbb_fw_set_reg_cmn() argument
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| H A D | halbb_api.c | 18 void halbb_dyn_1r_cca_en(struct bb_info *bb, bool en) in halbb_dyn_1r_cca_en() argument
20 switch (bb->ic_type) { in halbb_dyn_1r_cca_en()
24 halbb_dyn_1r_cca_en_8852a_2(bb, en); in halbb_dyn_1r_cca_en()
32 u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx) in halbb_wifi_event_notify() argument
34 struct rtw_hw_band *hw_band = &bb->hal_com->band[phy_idx]; in halbb_wifi_event_notify()
39 BB_DBG(bb, DBG_DIG, "[%s] event=%d\n", __func__, event); in halbb_wifi_event_notify()
47 pause_result = halbb_pause_func(bb, F_DIG, HALBB_PAUSE, HALBB_PAUSE_LV_2, 2, val); in halbb_wifi_event_notify()
48 halbb_edcca_event_nofity(bb, HALBB_PAUSE); in halbb_wifi_event_notify()
50 pause_result = halbb_pause_func(bb, F_DIG, HALBB_RESUME, HALBB_PAUSE_LV_2, 2, val); in halbb_wifi_event_notify()
51 halbb_edcca_event_nofity(bb, HALBB_RESUME); in halbb_wifi_event_notify()
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| H A D | halbb_pmac_setting.c | 28 void halbb_set_pmac_tx(struct bb_info *bb, struct halbb_pmac_info *tx_info, in halbb_set_pmac_tx() argument
32 BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); in halbb_set_pmac_tx()
34 switch (bb->ic_type) { in halbb_set_pmac_tx()
38 halbb_set_pmac_tx_8852a(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
44 halbb_set_pmac_tx_8852a_2(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
50 halbb_set_pmac_tx_8852b(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
56 halbb_set_pmac_tx_8852c(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
64 void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_set_tmac_tx() argument
66 switch (bb->ic_type) { in halbb_set_tmac_tx()
70 halbb_set_tmac_tx_8852a(bb, phy_idx); in halbb_set_tmac_tx()
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| H A D | halbb_psd.c | 31 void halbb_psd_igi_lv(struct bb_info *bb, enum igi_lv_sel igi_lv) in halbb_psd_igi_lv() argument
33 struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; in halbb_psd_igi_lv()
37 halbb_set_reg(bb, 0x1590, 0x7000, psd->lna_bkp); in halbb_psd_igi_lv()
38 halbb_set_reg(bb, 0x1650, 0x7000, psd->lna_bkp_b); in halbb_psd_igi_lv()
39 halbb_set_reg(bb, 0x1598, BIT(20), psd->tia_bkp); in halbb_psd_igi_lv()
40 halbb_set_reg(bb, 0x1658, BIT(20), psd->tia_bkp_b); in halbb_psd_igi_lv()
41 halbb_set_reg(bb, 0x1580, 0x3e0, psd->rxbb_bkp); in halbb_psd_igi_lv()
42 halbb_set_reg(bb, 0x1640, 0x3e0, psd->rxbb_bkp_b); in halbb_psd_igi_lv()
45 halbb_set_reg(bb, 0x1590, 0x7000, 0x6); in halbb_psd_igi_lv()
46 halbb_set_reg(bb, 0x1650, 0x7000, 0x6); in halbb_psd_igi_lv()
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| H A D | halbb_cfo_trk.c | 31 void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en) in halbb_dyn_cfo_trk_loop_en() argument
33 bb->bb_cfo_trk_i.bb_dyn_cfo_trk_lop_i.dyn_cfo_trk_loop_en = en; in halbb_dyn_cfo_trk_loop_en()
36 void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state) in halbb_cfo_trk_loop_cr_cfg() argument
38 struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; in halbb_cfo_trk_loop_cr_cfg()
47 BB_DBG(bb, DBG_IC_API, "hold_cnt = %d", dctl->dctl_hold_cnt); in halbb_cfo_trk_loop_cr_cfg()
56 halbb_set_reg(bb, 0x4404, 0x7C00, cr->dctl_data); /*8852a CR*/ in halbb_cfo_trk_loop_cr_cfg()
57 halbb_set_reg(bb, 0x440c, 0x7C00, cr->dctl_pilot); in halbb_cfo_trk_loop_cr_cfg()
59 BB_DBG(bb, DBG_IC_API, "dctl_data = 0x%x, dctl_pilot = 0x%x", cr->dctl_data, cr->dctl_pilot); in halbb_cfo_trk_loop_cr_cfg()
62 void halbb_dyn_cfo_trk_loop(struct bb_info *bb) in halbb_dyn_cfo_trk_loop() argument
64 struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; in halbb_dyn_cfo_trk_loop()
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| H A D | halbb_interface.h | 33 #define HALBB_SET_CR_CMN(bb, cr, val, phy_idx) halbb_set_reg_cmn(bb, cr, cr##_M, val, phy_idx); argument
34 #define HALBB_SET_CR(bb, cr, val) halbb_set_reg(bb, cr, cr##_M, val); argument
36 #define HALBB_GET_CR_CMN(bb, cr, val, phy_idx) halbb_get_reg_cmn(bb, cr, cr##_M, phy_idx); argument
37 #define HALBB_GET_CR(bb, cr) halbb_get_reg(bb, cr, cr##_M); argument
39 #define halbb_get_32(bb, addr) hal_read32((bb)->hal_com, (addr | BB_OFST)) argument
40 #define halbb_get_16(bb, addr) hal_read16((bb)->hal_com, (addr | BB_OFST)) argument
41 #define halbb_get_8(bb, addr) hal_read8((bb)->hal_com, (addr | BB_OFST)) argument
42 #define halbb_set_32(bb, addr, val) hal_write32((bb)->hal_com, (addr | BB_OFST), val) argument
43 #define halbb_set_16(bb, addr, val) hal_write16((bb)->hal_com, (addr | BB_OFST), val) argument
44 #define halbb_set_8(bb, addr, val) hal_write8((bb)->hal_com, (addr | BB_OFST), val) argument
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| H A D | halbb_mp.c | 27 u16 halbb_mp_get_tx_ok(struct bb_info *bb, u32 rate_index, in halbb_mp_get_tx_ok() argument
32 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_tx_ok()
34 if (halbb_is_cck_rate(bb, (u16)rate_index)) in halbb_mp_get_tx_ok()
35 tx_ok = halbb_get_reg(bb, cr->cnt_ccktxon, cr->cnt_ccktxon_m); in halbb_mp_get_tx_ok()
37 tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx); in halbb_mp_get_tx_ok()
41 u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_mp_get_rx_crc_ok() argument
46 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_rx_crc_ok()
49 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p0, cr->cnt_cck_crc32ok_p0_m); in halbb_mp_get_rx_crc_ok()
51 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p1, cr->cnt_cck_crc32ok_p1_m); in halbb_mp_get_rx_crc_ok()
53 ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
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| H A D | halbb.c | 27 void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used, in halbb_supportability_dbg() argument
42 pre_support_ability = bb->support_ability; in halbb_supportability_dbg()
43 comp = bb->support_ability; in halbb_supportability_dbg()
94 bb->support_ability = 0; in halbb_supportability_dbg()
99 bb->support_ability |= (one << val[0]); in halbb_supportability_dbg()
101 bb->support_ability &= ~(one << val[0]); in halbb_supportability_dbg()
110 "Cur-supportability = 0x%llx\n", bb->support_ability); in halbb_supportability_dbg()
118 bool halbb_sta_info_init(struct bb_info *bb, in halbb_sta_info_init() argument
123 if (!bb) { in halbb_sta_info_init()
134 bb_sta = halbb_mem_alloc(bb, sizeof(struct bb_sta_info)); in halbb_sta_info_init()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/ |
| H A D | halbb_init.c | 17 bool halbb_chk_bb_rf_pkg_set_valid(struct bb_info *bb) in halbb_chk_bb_rf_pkg_set_valid() argument
19 struct rtw_hal_com_t *hal_i = bb->hal_com; in halbb_chk_bb_rf_pkg_set_valid()
24 switch (bb->ic_type) { in halbb_chk_bb_rf_pkg_set_valid()
27 valid = halbb_chk_pkg_valid_8852a(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
33 valid = halbb_chk_pkg_valid_8852a_2(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
39 valid = halbb_chk_pkg_valid_8852b(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
45 valid = halbb_chk_pkg_valid_8852c(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
51 valid = halbb_chk_pkg_valid_8834a(bb, bb_ver, rf_ver); in halbb_chk_bb_rf_pkg_set_valid()
63 void halbb_ic_hw_setting_init(struct bb_info *bb) in halbb_ic_hw_setting_init() argument
66 halbb_tdma_cr_sel_init(bb); in halbb_ic_hw_setting_init()
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| H A D | halbb_fwofld.c | 28 bool halbb_check_fw_ofld(struct bb_info *bb) in halbb_check_fw_ofld() argument
30 bool ret = bb->phl_com->dev_cap.fw_cap.offload_cap & BIT0; in halbb_check_fw_ofld()
32 BB_DBG(bb, DBG_FW_INFO, "FW ofld ret = %d\n", (u8)ret); in halbb_check_fw_ofld()
36 bool halbb_fw_delay(struct bb_info *bb, u32 val) in halbb_fw_delay() argument
45 ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd); in halbb_fw_delay()
46 BB_DBG(bb, DBG_FW_INFO, "FW ofld delay:%x\n", val); in halbb_fw_delay()
56 bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lc) in halbb_fw_set_reg() argument
68 ret = rtw_hal_mac_add_cmd_ofld(bb->hal_com, &cmd); in halbb_fw_set_reg()
69 BB_DBG(bb, DBG_FW_INFO, "FW ofld addr:%x, val:%x, msk:%x\n", addr, val, mask); in halbb_fw_set_reg()
80 bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, in halbb_fw_set_reg_cmn() argument
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| H A D | halbb_api.c | 18 void halbb_dyn_1r_cca_en(struct bb_info *bb, bool en) in halbb_dyn_1r_cca_en() argument
20 switch (bb->ic_type) { in halbb_dyn_1r_cca_en()
24 halbb_dyn_1r_cca_en_8852a_2(bb, en); in halbb_dyn_1r_cca_en()
32 u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx) in halbb_wifi_event_notify() argument
34 struct rtw_hw_band *hw_band = &bb->hal_com->band[phy_idx]; in halbb_wifi_event_notify()
39 BB_DBG(bb, DBG_DIG, "[%s] event=%d\n", __func__, event); in halbb_wifi_event_notify()
47 pause_result = halbb_pause_func(bb, F_DIG, HALBB_PAUSE, HALBB_PAUSE_LV_2, 2, val); in halbb_wifi_event_notify()
48 halbb_edcca_event_nofity(bb, HALBB_PAUSE); in halbb_wifi_event_notify()
50 pause_result = halbb_pause_func(bb, F_DIG, HALBB_RESUME, HALBB_PAUSE_LV_2, 2, val); in halbb_wifi_event_notify()
51 halbb_edcca_event_nofity(bb, HALBB_RESUME); in halbb_wifi_event_notify()
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| H A D | halbb_pmac_setting.c | 28 void halbb_set_pmac_tx(struct bb_info *bb, struct halbb_pmac_info *tx_info, in halbb_set_pmac_tx() argument
32 BB_DBG(bb, DBG_PHY_CONFIG, "<====== %s ======>\n", __func__); in halbb_set_pmac_tx()
34 switch (bb->ic_type) { in halbb_set_pmac_tx()
38 halbb_set_pmac_tx_8852a(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
44 halbb_set_pmac_tx_8852a_2(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
50 halbb_set_pmac_tx_8852b(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
56 halbb_set_pmac_tx_8852c(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
64 void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_set_tmac_tx() argument
66 switch (bb->ic_type) { in halbb_set_tmac_tx()
70 halbb_set_tmac_tx_8852a(bb, phy_idx); in halbb_set_tmac_tx()
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| H A D | halbb_psd.c | 31 void halbb_psd_igi_lv(struct bb_info *bb, enum igi_lv_sel igi_lv) in halbb_psd_igi_lv() argument
33 struct bb_psd_info *psd = &bb->bb_cmn_hooker->bb_psd_i; in halbb_psd_igi_lv()
37 halbb_set_reg(bb, 0x1590, 0x7000, psd->lna_bkp); in halbb_psd_igi_lv()
38 halbb_set_reg(bb, 0x1650, 0x7000, psd->lna_bkp_b); in halbb_psd_igi_lv()
39 halbb_set_reg(bb, 0x1598, BIT(20), psd->tia_bkp); in halbb_psd_igi_lv()
40 halbb_set_reg(bb, 0x1658, BIT(20), psd->tia_bkp_b); in halbb_psd_igi_lv()
41 halbb_set_reg(bb, 0x1580, 0x3e0, psd->rxbb_bkp); in halbb_psd_igi_lv()
42 halbb_set_reg(bb, 0x1640, 0x3e0, psd->rxbb_bkp_b); in halbb_psd_igi_lv()
45 halbb_set_reg(bb, 0x1590, 0x7000, 0x6); in halbb_psd_igi_lv()
46 halbb_set_reg(bb, 0x1650, 0x7000, 0x6); in halbb_psd_igi_lv()
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| H A D | halbb_cfo_trk.c | 31 void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en) in halbb_dyn_cfo_trk_loop_en() argument
33 bb->bb_cfo_trk_i.bb_dyn_cfo_trk_lop_i.dyn_cfo_trk_loop_en = en; in halbb_dyn_cfo_trk_loop_en()
36 void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state) in halbb_cfo_trk_loop_cr_cfg() argument
38 struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; in halbb_cfo_trk_loop_cr_cfg()
47 BB_DBG(bb, DBG_IC_API, "hold_cnt = %d", dctl->dctl_hold_cnt); in halbb_cfo_trk_loop_cr_cfg()
56 halbb_set_reg(bb, 0x4404, 0x7C00, cr->dctl_data); /*8852a CR*/ in halbb_cfo_trk_loop_cr_cfg()
57 halbb_set_reg(bb, 0x440c, 0x7C00, cr->dctl_pilot); in halbb_cfo_trk_loop_cr_cfg()
59 BB_DBG(bb, DBG_IC_API, "dctl_data = 0x%x, dctl_pilot = 0x%x", cr->dctl_data, cr->dctl_pilot); in halbb_cfo_trk_loop_cr_cfg()
62 void halbb_dyn_cfo_trk_loop(struct bb_info *bb) in halbb_dyn_cfo_trk_loop() argument
64 struct bb_cfo_trk_info *cfo_trk = &bb->bb_cfo_trk_i; in halbb_dyn_cfo_trk_loop()
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| H A D | halbb_interface.h | 33 #define HALBB_SET_CR_CMN(bb, cr, val, phy_idx) halbb_set_reg_cmn(bb, cr, cr##_M, val, phy_idx); argument
34 #define HALBB_SET_CR(bb, cr, val) halbb_set_reg(bb, cr, cr##_M, val); argument
36 #define HALBB_GET_CR_CMN(bb, cr, val, phy_idx) halbb_get_reg_cmn(bb, cr, cr##_M, phy_idx); argument
37 #define HALBB_GET_CR(bb, cr) halbb_get_reg(bb, cr, cr##_M); argument
39 #define halbb_get_32(bb, addr) hal_read32((bb)->hal_com, (addr | BB_OFST)) argument
40 #define halbb_get_16(bb, addr) hal_read16((bb)->hal_com, (addr | BB_OFST)) argument
41 #define halbb_get_8(bb, addr) hal_read8((bb)->hal_com, (addr | BB_OFST)) argument
42 #define halbb_set_32(bb, addr, val) hal_write32((bb)->hal_com, (addr | BB_OFST), val) argument
43 #define halbb_set_16(bb, addr, val) hal_write16((bb)->hal_com, (addr | BB_OFST), val) argument
44 #define halbb_set_8(bb, addr, val) hal_write8((bb)->hal_com, (addr | BB_OFST), val) argument
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| H A D | halbb_mp.c | 27 u16 halbb_mp_get_tx_ok(struct bb_info *bb, u32 rate_index, in halbb_mp_get_tx_ok() argument
32 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_tx_ok()
34 if (halbb_is_cck_rate(bb, (u16)rate_index)) in halbb_mp_get_tx_ok()
35 tx_ok = halbb_get_reg(bb, cr->cnt_ccktxon, cr->cnt_ccktxon_m); in halbb_mp_get_tx_ok()
37 tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx); in halbb_mp_get_tx_ok()
41 u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_mp_get_rx_crc_ok() argument
46 struct bb_rpt_cr_info *cr = &bb->bb_rpt_i.bb_rpt_cr_i; in halbb_mp_get_rx_crc_ok()
49 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p0, cr->cnt_cck_crc32ok_p0_m); in halbb_mp_get_rx_crc_ok()
51 cck_ok = halbb_get_reg(bb, cr->cnt_cck_crc32ok_p1, cr->cnt_cck_crc32ok_p1_m); in halbb_mp_get_rx_crc_ok()
53 ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
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| H A D | halbb.c | 27 void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used, in halbb_supportability_dbg() argument
42 pre_support_ability = bb->support_ability; in halbb_supportability_dbg()
43 comp = bb->support_ability; in halbb_supportability_dbg()
94 bb->support_ability = 0; in halbb_supportability_dbg()
99 bb->support_ability |= (one << val[0]); in halbb_supportability_dbg()
101 bb->support_ability &= ~(one << val[0]); in halbb_supportability_dbg()
110 "Cur-supportability = 0x%llx\n", bb->support_ability); in halbb_supportability_dbg()
118 bool halbb_sta_info_init(struct bb_info *bb, in halbb_sta_info_init() argument
123 if (!bb) { in halbb_sta_info_init()
134 bb_sta = halbb_mem_alloc(bb, sizeof(struct bb_sta_info)); in halbb_sta_info_init()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/ |
| H A D | halbb_8852b_api.c | 29 bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb, in halbb_set_pwr_ul_tb_ofst_8852b() argument
39 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1); in halbb_set_pwr_ul_tb_ofst_8852b()
42 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst); in halbb_set_pwr_ul_tb_ofst_8852b()
47 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3); in halbb_set_pwr_ul_tb_ofst_8852b()
52 void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx, in halbb_tx_triangular_shap_cfg_8852b() argument
55 halbb_set_reg(bb, 0x4494, 0x3000000, shape_idx); in halbb_tx_triangular_shap_cfg_8852b()
59 void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx, in halbb_tx_dfir_shap_cck_8852b() argument
71 BB_DBG(bb, DBG_DBG_API, "[%s] ch=%d, shape_idx=%d\n", __func__, ch, shape_idx); in halbb_tx_dfir_shap_cck_8852b()
89 halbb_set_reg_cmn(bb, 0x2300 + (i << 2), MASKDWORD, para[i], phy_idx); in halbb_tx_dfir_shap_cck_8852b()
90 BB_DBG(bb, DBG_DBG_API, "Reg0x%08x = 0x%08x\n", 0x2300 + (i << 2), para[i]); in halbb_tx_dfir_shap_cck_8852b()
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| H A D | halbb_8852b_fwofld_api.c | 29 bool halbb_fwcfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data, in halbb_fwcfg_bb_phy_8852b() argument
35 halbb_delay_ms(bb, 50); in halbb_fwcfg_bb_phy_8852b()
36 BB_DBG(bb, DBG_INIT, "Delay 50 ms\n"); in halbb_fwcfg_bb_phy_8852b()
38 halbb_delay_ms(bb, 5); in halbb_fwcfg_bb_phy_8852b()
39 BB_DBG(bb, DBG_INIT, "Delay 5 ms\n"); in halbb_fwcfg_bb_phy_8852b()
41 halbb_delay_ms(bb, 1); in halbb_fwcfg_bb_phy_8852b()
42 BB_DBG(bb, DBG_INIT, "Delay 1 ms\n"); in halbb_fwcfg_bb_phy_8852b()
44 halbb_delay_us(bb, 50); in halbb_fwcfg_bb_phy_8852b()
45 BB_DBG(bb, DBG_INIT, "Delay 50 us\n"); in halbb_fwcfg_bb_phy_8852b()
47 halbb_delay_us(bb, 5); in halbb_fwcfg_bb_phy_8852b()
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| H A D | halbb_8852b.c | 29 bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver) in halbb_chk_pkg_valid_8852b() argument
52 void halbb_stop_pmac_tx_8852b(struct bb_info *bb, in halbb_stop_pmac_tx_8852b() argument
58 halbb_set_reg(bb, 0x2300, BIT(26), 1); in halbb_stop_pmac_tx_8852b()
59 halbb_set_reg(bb, 0x2338, BIT(17), 0); in halbb_stop_pmac_tx_8852b()
60 halbb_set_reg(bb, 0x2300, BIT(28), 0); in halbb_stop_pmac_tx_8852b()
61 halbb_set_reg(bb, 0x2300, BIT(26), 0); in halbb_stop_pmac_tx_8852b()
63 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
67 halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
69 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
74 void halbb_start_pmac_tx_8852b(struct bb_info *bb, in halbb_start_pmac_tx_8852b() argument
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/ |
| H A D | halbb_8852b_api.c | 29 bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb, in halbb_set_pwr_ul_tb_ofst_8852b() argument
39 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1); in halbb_set_pwr_ul_tb_ofst_8852b()
42 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst); in halbb_set_pwr_ul_tb_ofst_8852b()
47 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3); in halbb_set_pwr_ul_tb_ofst_8852b()
52 void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx, in halbb_tx_triangular_shap_cfg_8852b() argument
55 halbb_set_reg(bb, 0x4494, 0x3000000, shape_idx); in halbb_tx_triangular_shap_cfg_8852b()
59 void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx, in halbb_tx_dfir_shap_cck_8852b() argument
71 BB_DBG(bb, DBG_DBG_API, "[%s] ch=%d, shape_idx=%d\n", __func__, ch, shape_idx); in halbb_tx_dfir_shap_cck_8852b()
89 halbb_set_reg_cmn(bb, 0x2300 + (i << 2), MASKDWORD, para[i], phy_idx); in halbb_tx_dfir_shap_cck_8852b()
90 BB_DBG(bb, DBG_DBG_API, "Reg0x%08x = 0x%08x\n", 0x2300 + (i << 2), para[i]); in halbb_tx_dfir_shap_cck_8852b()
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| H A D | halbb_8852b_fwofld_api.c | 29 bool halbb_fwcfg_bb_phy_8852b(struct bb_info *bb, u32 addr, u32 data, in halbb_fwcfg_bb_phy_8852b() argument
35 halbb_delay_ms(bb, 50); in halbb_fwcfg_bb_phy_8852b()
36 BB_DBG(bb, DBG_INIT, "Delay 50 ms\n"); in halbb_fwcfg_bb_phy_8852b()
38 halbb_delay_ms(bb, 5); in halbb_fwcfg_bb_phy_8852b()
39 BB_DBG(bb, DBG_INIT, "Delay 5 ms\n"); in halbb_fwcfg_bb_phy_8852b()
41 halbb_delay_ms(bb, 1); in halbb_fwcfg_bb_phy_8852b()
42 BB_DBG(bb, DBG_INIT, "Delay 1 ms\n"); in halbb_fwcfg_bb_phy_8852b()
44 halbb_delay_us(bb, 50); in halbb_fwcfg_bb_phy_8852b()
45 BB_DBG(bb, DBG_INIT, "Delay 50 us\n"); in halbb_fwcfg_bb_phy_8852b()
47 halbb_delay_us(bb, 5); in halbb_fwcfg_bb_phy_8852b()
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| H A D | halbb_8852b.c | 29 bool halbb_chk_pkg_valid_8852b(struct bb_info *bb, u8 bb_ver, u8 rf_ver) in halbb_chk_pkg_valid_8852b() argument
52 void halbb_stop_pmac_tx_8852b(struct bb_info *bb, in halbb_stop_pmac_tx_8852b() argument
58 halbb_set_reg(bb, 0x2300, BIT(26), 1); in halbb_stop_pmac_tx_8852b()
59 halbb_set_reg(bb, 0x2338, BIT(17), 0); in halbb_stop_pmac_tx_8852b()
60 halbb_set_reg(bb, 0x2300, BIT(28), 0); in halbb_stop_pmac_tx_8852b()
61 halbb_set_reg(bb, 0x2300, BIT(26), 0); in halbb_stop_pmac_tx_8852b()
63 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
67 halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
69 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
74 void halbb_start_pmac_tx_8852b(struct bb_info *bb, in halbb_start_pmac_tx_8852b() argument
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| H A D | halbb_8852b_api.h | 47 bool halbb_set_pwr_ul_tb_ofst_8852b(struct bb_info *bb,
49 void halbb_tx_triangular_shap_cfg_8852b(struct bb_info *bb, u8 shape_idx,
51 void halbb_tx_dfir_shap_cck_8852b(struct bb_info *bb, u8 ch, u8 shape_idx,
53 bool halbb_ctrl_bw_ch_8852b(struct bb_info *bb, u8 pri_ch, u8 central_ch,
57 bool halbb_ctrl_rx_path_8852b(struct bb_info *bb, enum rf_path rx_path);
59 bool halbb_ctrl_tx_path_8852b(struct bb_info *bb, enum rf_path tx_path);
63 void halbb_gpio_ctrl_dump_8852b(struct bb_info *bb);
65 void halbb_gpio_rfm_8852b(struct bb_info *bb, enum bb_path path,
69 void halbb_gpio_trsw_table_8852b(struct bb_info *bb, enum bb_path path,
73 void halbb_gpio_setting_8852b(struct bb_info *bb, u8 gpio_idx,
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