Searched refs:XGMAC_DMA_CH_TX_CONTROL (Results 1 – 2 of 2) sorted by relevance
71 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()75 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()281 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()283 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()294 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()296 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()476 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()483 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()531 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs()538 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs()[all …]
370 #define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x))) macro