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Searched refs:WR_ACCESS_OFFSET (Results 1 – 2 of 2) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c22 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ macro
93 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in peri_clk_enable()
155 writel(0, base + WR_ACCESS_OFFSET); in peri_clk_enable()
269 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
314 writel(0, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
345 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in bus_clk_enable()
369 writel(0, base + WR_ACCESS_OFFSET); in bus_clk_enable()
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c22 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ macro
93 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in peri_clk_enable()
155 writel(0, base + WR_ACCESS_OFFSET); in peri_clk_enable()
269 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
314 writel(0, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
345 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in bus_clk_enable()
369 writel(0, base + WR_ACCESS_OFFSET); in bus_clk_enable()