Searched refs:VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER (Results 1 – 2 of 2) sorted by relevance
267 #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER 0x000000e5 /* 229 */ macro
383 … = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER… in dce_virtual_sw_init()712 [VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER]; in dce_virtual_vblank_timer_handle()