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Searched refs:UVD_MPC_SET_MUX__SET_1__SHIFT (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h635 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
H A Duvd_3_1_sh_mask.h512 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
H A Duvd_4_0_sh_mask.h531 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003 macro
H A Duvd_4_2_sh_mask.h516 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
H A Duvd_5_0_sh_mask.h548 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
H A Duvd_6_0_sh_mask.h550 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1142 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2883 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2648 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3956 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c843 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v1_0_start_spg_mode()
1026 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_5.c836 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_5_start_dpg_mode()
990 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_5_start()
H A Dvcn_v2_0.c858 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_0_start_dpg_mode()
993 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_0_start()
H A Dvcn_v3_0.c960 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v3_0_start_dpg_mode()
1117 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v3_0_start()