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Searched refs:THM_BASE (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dnavi10_reg_init.c48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in navi10_reg_base_init()
H A Dnavi12_reg_init.c48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in navi12_reg_base_init()
H A Dnavi14_reg_init.c48 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in navi14_reg_base_init()
H A Dsienna_cichlid_reg_init.c51 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in sienna_cichlid_reg_base_init()
H A Darct_reg_init.c53 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in arct_reg_base_init()
H A Dvega10_reg_init.c52 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c50 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); in vega20_reg_base_init()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/
H A Dnavi10_ip_offset.h121 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, variable
H A Dnavi12_ip_offset.h165 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
H A Dnavi14_ip_offset.h165 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
H A Dvega20_ip_offset.h129 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, variable
H A Dsienna_cichlid_ip_offset.h172 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
H A Dvega10_ip_offset.h188 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, variable
H A Drenoir_ip_offset.h205 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, variable
H A Darct_ip_offset.h205 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, variable