Searched refs:TEGRA186_CLK_PLLP_OUT0 (Results 1 – 3 of 3) sorted by relevance
747 #define TEGRA186_CLK_PLLP_OUT0 269 macro
748 #define TEGRA186_CLK_PLLP_OUT0 269 macro
576 <&bpmp TEGRA186_CLK_PLLP_OUT0>;577 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;