1 /* -*- buffer-read-only: t -*-
2    Generated automatically by parsecpu.awk from arm-cpus.in.
3    Do not edit.
4 
5    Copyright (C) 2011-2020 Free Software Foundation, Inc.
6 
7    This file is part of GCC.
8 
9    GCC is free software; you can redistribute it and/or modify
10    it under the terms of the GNU General Public License as
11    published by the Free Software Foundation; either version 3,
12    or (at your option) any later version.
13 
14    GCC is distributed in the hope that it will be useful,
15    but WITHOUT ANY WARRANTY; without even the implied warranty of
16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17    GNU General Public License for more details.
18 
19    You should have received a copy of the GNU General Public
20    License along with GCC; see the file COPYING3.  If not see
21    <http://www.gnu.org/licenses/>.  */
22 
23 enum processor_type
24 {
25   TARGET_CPU_arm8,
26   TARGET_CPU_arm810,
27   TARGET_CPU_strongarm,
28   TARGET_CPU_fa526,
29   TARGET_CPU_fa626,
30   TARGET_CPU_arm7tdmi,
31   TARGET_CPU_arm710t,
32   TARGET_CPU_arm9,
33   TARGET_CPU_arm9tdmi,
34   TARGET_CPU_arm920t,
35   TARGET_CPU_arm10tdmi,
36   TARGET_CPU_arm9e,
37   TARGET_CPU_arm10e,
38   TARGET_CPU_xscale,
39   TARGET_CPU_iwmmxt,
40   TARGET_CPU_iwmmxt2,
41   TARGET_CPU_fa606te,
42   TARGET_CPU_fa626te,
43   TARGET_CPU_fmp626,
44   TARGET_CPU_fa726te,
45   TARGET_CPU_arm926ejs,
46   TARGET_CPU_arm1026ejs,
47   TARGET_CPU_arm1136js,
48   TARGET_CPU_arm1136jfs,
49   TARGET_CPU_arm1176jzs,
50   TARGET_CPU_arm1176jzfs,
51   TARGET_CPU_mpcorenovfp,
52   TARGET_CPU_mpcore,
53   TARGET_CPU_arm1156t2s,
54   TARGET_CPU_arm1156t2fs,
55   TARGET_CPU_cortexm1,
56   TARGET_CPU_cortexm0,
57   TARGET_CPU_cortexm0plus,
58   TARGET_CPU_cortexm1smallmultiply,
59   TARGET_CPU_cortexm0smallmultiply,
60   TARGET_CPU_cortexm0plussmallmultiply,
61   TARGET_CPU_genericv7a,
62   TARGET_CPU_cortexa5,
63   TARGET_CPU_cortexa7,
64   TARGET_CPU_cortexa8,
65   TARGET_CPU_cortexa9,
66   TARGET_CPU_cortexa12,
67   TARGET_CPU_cortexa15,
68   TARGET_CPU_cortexa17,
69   TARGET_CPU_cortexr4,
70   TARGET_CPU_cortexr4f,
71   TARGET_CPU_cortexr5,
72   TARGET_CPU_cortexr7,
73   TARGET_CPU_cortexr8,
74   TARGET_CPU_cortexm7,
75   TARGET_CPU_cortexm4,
76   TARGET_CPU_cortexm3,
77   TARGET_CPU_marvell_pj4,
78   TARGET_CPU_cortexa15cortexa7,
79   TARGET_CPU_cortexa17cortexa7,
80   TARGET_CPU_cortexa32,
81   TARGET_CPU_cortexa35,
82   TARGET_CPU_cortexa53,
83   TARGET_CPU_cortexa57,
84   TARGET_CPU_cortexa72,
85   TARGET_CPU_cortexa73,
86   TARGET_CPU_exynosm1,
87   TARGET_CPU_xgene1,
88   TARGET_CPU_cortexa57cortexa53,
89   TARGET_CPU_cortexa72cortexa53,
90   TARGET_CPU_cortexa73cortexa35,
91   TARGET_CPU_cortexa73cortexa53,
92   TARGET_CPU_cortexa55,
93   TARGET_CPU_cortexa75,
94   TARGET_CPU_cortexa76,
95   TARGET_CPU_cortexa76ae,
96   TARGET_CPU_cortexa77,
97   TARGET_CPU_neoversen1,
98   TARGET_CPU_cortexa75cortexa55,
99   TARGET_CPU_cortexa76cortexa55,
100   TARGET_CPU_neoversev1,
101   TARGET_CPU_neoversen2,
102   TARGET_CPU_cortexm23,
103   TARGET_CPU_cortexm33,
104   TARGET_CPU_cortexm35p,
105   TARGET_CPU_cortexm55,
106   TARGET_CPU_cortexr52,
107   TARGET_CPU_arm_none
108 };
109 
110 enum arch_type
111 {
112   TARGET_ARCH_armv4,
113   TARGET_ARCH_armv4t,
114   TARGET_ARCH_armv5t,
115   TARGET_ARCH_armv5te,
116   TARGET_ARCH_armv5tej,
117   TARGET_ARCH_armv6,
118   TARGET_ARCH_armv6j,
119   TARGET_ARCH_armv6k,
120   TARGET_ARCH_armv6z,
121   TARGET_ARCH_armv6kz,
122   TARGET_ARCH_armv6zk,
123   TARGET_ARCH_armv6t2,
124   TARGET_ARCH_armv6_m,
125   TARGET_ARCH_armv6s_m,
126   TARGET_ARCH_armv7,
127   TARGET_ARCH_armv7_a,
128   TARGET_ARCH_armv7ve,
129   TARGET_ARCH_armv7_r,
130   TARGET_ARCH_armv7_m,
131   TARGET_ARCH_armv7e_m,
132   TARGET_ARCH_armv8_a,
133   TARGET_ARCH_armv8_1_a,
134   TARGET_ARCH_armv8_2_a,
135   TARGET_ARCH_armv8_3_a,
136   TARGET_ARCH_armv8_4_a,
137   TARGET_ARCH_armv8_5_a,
138   TARGET_ARCH_armv8_6_a,
139   TARGET_ARCH_armv8_m_base,
140   TARGET_ARCH_armv8_m_main,
141   TARGET_ARCH_armv8_r,
142   TARGET_ARCH_armv8_1_m_main,
143   TARGET_ARCH_iwmmxt,
144   TARGET_ARCH_iwmmxt2,
145   TARGET_ARCH_arm_none
146 };
147 
148 enum fpu_type
149 {
150   TARGET_FPU_vfp,
151   TARGET_FPU_vfpv2,
152   TARGET_FPU_vfpv3,
153   TARGET_FPU_vfpv3_fp16,
154   TARGET_FPU_vfpv3_d16,
155   TARGET_FPU_vfpv3_d16_fp16,
156   TARGET_FPU_vfpv3xd,
157   TARGET_FPU_vfpv3xd_fp16,
158   TARGET_FPU_neon,
159   TARGET_FPU_neon_vfpv3,
160   TARGET_FPU_neon_fp16,
161   TARGET_FPU_vfpv4,
162   TARGET_FPU_neon_vfpv4,
163   TARGET_FPU_vfpv4_d16,
164   TARGET_FPU_fpv4_sp_d16,
165   TARGET_FPU_fpv5_sp_d16,
166   TARGET_FPU_fpv5_d16,
167   TARGET_FPU_fp_armv8,
168   TARGET_FPU_neon_fp_armv8,
169   TARGET_FPU_crypto_neon_fp_armv8,
170   TARGET_FPU_vfp3,
171   TARGET_FPU_auto
172 };
173