Searched refs:SSSR_D11_RESET_SEQ_STEPS (Results 1 – 11 of 11) sorted by relevance
22128 #define SSSR_D11_RESET_SEQ_STEPS 5u macro22194 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];22258 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];22322 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];22384 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];
22220 #define SSSR_D11_RESET_SEQ_STEPS 5u macro22286 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];22350 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];22414 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];22476 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];
17724 #define SSSR_D11_RESET_SEQ_STEPS 5 macro17786 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];17850 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];
17732 #define SSSR_D11_RESET_SEQ_STEPS 5 macro17794 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];17858 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];
910 for (j = 0; j < SSSR_D11_RESET_SEQ_STEPS; j++) { in dhd_dump_sssr_reg_info_v2()1003 for (j = 0; j < SSSR_D11_RESET_SEQ_STEPS; j++) { in dhd_dump_sssr_reg_info_v1()
13632 #define SSSR_D11_RESET_SEQ_STEPS 5 macro13693 uint32 ioctrl_resetseq_val[SSSR_D11_RESET_SEQ_STEPS];
619 for (j = 0; j < SSSR_D11_RESET_SEQ_STEPS; j++) { in dhd_dump_sssr_reg_info()
620 for (j = 0; j < SSSR_D11_RESET_SEQ_STEPS; j++) { in dhd_dump_sssr_reg_info()