Searched refs:SLOT_RB_SIZE (Results 1 – 5 of 5) sorted by relevance
27 #define SLOT_RB_SIZE 2 macro28 #define SLOT_RB_MASK (SLOT_RB_SIZE - 1)47 struct rb_entry entries[SLOT_RB_SIZE];
58 WARN_ON(SLOT_RB_ENTRIES(rb) >= SLOT_RB_SIZE); in kbase_gpu_enqueue_atom()152 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_gpu_atoms_submitted()180 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_gpu_atoms_submitted_any()197 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_backend_nr_atoms_submitted()215 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_backend_nr_atoms_on_slot()231 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_gpu_nr_atoms_on_slot_min()277 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_gpu_check_secure_atoms()299 return SLOT_RB_SIZE - kbase_backend_nr_atoms_on_slot(kbdev, js); in kbase_backend_slot_free()1033 for (idx = 0; idx < SLOT_RB_SIZE; idx++) { in kbase_backend_slot_update()1507 for (idx = 0; idx < SLOT_RB_SIZE; idx++) { in kbase_backend_reset()[all …]
30 #define SLOT_RB_SIZE 2 macro31 #define SLOT_RB_MASK (SLOT_RB_SIZE - 1)72 struct rb_entry entries[SLOT_RB_SIZE];
74 WARN_ON(SLOT_RB_ENTRIES(rb) >= SLOT_RB_SIZE); in kbase_gpu_enqueue_atom()151 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_gpu_atoms_submitted_any()168 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_backend_nr_atoms_submitted()186 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_backend_nr_atoms_on_slot()202 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_gpu_nr_atoms_on_slot_min()250 for (i = 0; i < SLOT_RB_SIZE; i++) { in kbase_gpu_check_secure_atoms()274 return SLOT_RB_SIZE - kbase_backend_nr_atoms_on_slot(kbdev, js); in kbase_backend_slot_free()867 for (idx = 0; idx < SLOT_RB_SIZE; idx++) { in kbase_backend_slot_update()1407 for (idx = 0; idx < SLOT_RB_SIZE; idx++) { in kbase_backend_reset()1828 for (idx = 0; idx < SLOT_RB_SIZE; idx++) { in kbase_gpu_dump_slots()
857 BUILD_BUG_ON(SLOT_RB_SIZE != 2); in kbasep_kinstr_jm_atom_hw_submit()878 BUILD_BUG_ON(SLOT_RB_SIZE != 2); in kbasep_kinstr_jm_atom_hw_release()