SET_CLR_WORD (reference) in projects: OK3568_Linux_fs

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Searched refs:SET_CLR_WORD (Results 1 – 25 of 53) sorted by relevance

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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/
H A D	rx_forwarding.c	133 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSA); in af_fwd_cfg() 136 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_REQ); in af_fwd_cfg() 139 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_RES); in af_fwd_cfg() 142 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELTS); in af_fwd_cfg() 145 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_REQ); in af_fwd_cfg() 148 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_RES); in af_fwd_cfg() 151 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELBA); in af_fwd_cfg() 154 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_NCW); in af_fwd_cfg() 157 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_GID_MGNT); in af_fwd_cfg() 160 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_OP_MODE); in af_fwd_cfg() [all …]
H A D	dbgport_hw.c	58 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 73 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 85 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 101 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 130 val32 = SET_CLR_WORD(val32, intn_val, B_AX_DBG_SEL); in dp_intn_idx_set() 147 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 249 val32 = SET_CLR_WORD(val32, intn_val, B_PL_AXIDMA_DBG_SEL); in dp_intn_idx_set() 357 val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG0_SEL); in dp_intn_idx_set() 358 val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG1_SEL); in dp_intn_idx_set() 451 val16 = SET_CLR_WORD(val16, intn_val, B_AX_PLE_DBG0_SEL); in dp_intn_idx_set() [all …]
H A D	dbgpkg.c	1975 val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC, in dbg_port_sel() 1980 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); in dbg_port_sel() 1981 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); in dbg_port_sel() 1985 val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); in dbg_port_sel() 1992 val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC, in dbg_port_sel() 1997 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); in dbg_port_sel() 1998 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); in dbg_port_sel() 2002 val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); in dbg_port_sel() 2009 val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_RMAC, in dbg_port_sel() 2014 val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); in dbg_port_sel() [all …]
H A D	mport.c	552 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 556 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 560 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 564 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 568 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 933 w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM); in _set_max_mbid_num() 940 w_val32 = SET_CLR_WORD(val32, subspc, B_AX_SUB_BCN_SPACE_P0); in _set_max_mbid_num() 942 w_val32 = SET_CLR_WORD(val32, 0, B_AX_SUB_BCN_SPACE_P0); in _set_max_mbid_num() 956 w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM); in port0_mbid_set() 989 w_val32 = SET_CLR_WORD(val32, subspc_u32, B_AX_SUB_BCN_SPACE_P0); in port0_subspc_set() [all …]
H A D	trxcfg.c	935 val32 = SET_CLR_WORD(val32, SIFS_MACTXEN_T1, B_AX_SIFS_MACTXEN_T1); in scheduler_init() 954 val32 = SET_CLR_WORD(val32, SCH_PREBKF_16US, B_AX_PREBKF_TIME); in scheduler_init() 960 val32 = SET_CLR_WORD(val32, 0x6a, B_AX_R_SIFS_AGGR_TIME); in scheduler_init() 966 val32 = SET_CLR_WORD(val32, SCH_PREBKF_24US, B_AX_PREBKF_TIME); in scheduler_init() 1050 val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_FPGA, in tmac_init() 1053 val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_DEF, in tmac_init() 1073 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_CCK, in trxptcl_init() 1076 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52A, in trxptcl_init() 1079 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52B, in trxptcl_init() 1082 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52C, in trxptcl_init() [all …]
H A D	spatial_reuse.c	`43 val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_min, in mac_sr_update() 45 val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_max, in mac_sr_update() 47 val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_min, in mac_sr_update() 49 val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_max, in mac_sr_update()`
H A D	cpuio.c	55 val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_WD_BUF_REQ_LEN); in mac_dle_buf_req_wd() 91 val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_PL_BUF_REQ_LEN); in mac_dle_buf_req_pl() 130 val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->start_pktid, in mac_set_cpuio_wd() 132 val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->end_pktid, in mac_set_cpuio_wd() 137 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_pid, in mac_set_cpuio_wd() 139 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_qid, in mac_set_cpuio_wd() 141 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_pid, in mac_set_cpuio_wd() 143 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_qid, in mac_set_cpuio_wd() 148 val_op0 = SET_CLR_WORD(val_op0, cmd_type, in mac_set_cpuio_wd() 150 val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->macid, in mac_set_cpuio_wd() [all …]
H A D	coex.c	119 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3, in mac_coex_init() 143 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE); in mac_coex_init() 223 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3, in mac_coex_init() 231 val = SET_CLR_WORD(val, MAC_AX_RTK_RATE, in mac_coex_init() 237 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE); in mac_coex_init() 241 val16 = SET_CLR_WORD(val16, MAC_AX_CSR_PRI_TO, in mac_coex_init() 243 val16 = SET_CLR_WORD(val16, MAC_AX_CSR_TRX_TO, in mac_coex_init() 245 val16 = SET_CLR_WORD(val16, MAC_AX_CSR_DELAY, in mac_coex_init()
H A D	hwamsdu.c	`171 val = SET_CLR_WORD(val, low_th, B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH); in mac_enable_cut_hwamsdu() 172 val = (SET_CLR_WORD(val, high_th, B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH) \| in mac_enable_cut_hwamsdu() 182 val = (SET_CLR_WORD(val, aligned, B_AX_EXTRA_SHIFT)); in mac_enable_cut_hwamsdu() 210 val = (SET_CLR_WORD(val, max_num, B_AX_MAX_AMSDU_NUM) \| in mac_enable_hwmasdu()`
H A D	_pcie.c	637 val32 = SET_CLR_WORD(val32, r_addr, B_AX_DBI_ADDR); in dbi_r32_pcie() 678 val32 = SET_CLR_WORD(val32, w_addr, B_AX_DBI_ADDR); in dbi_w32_pcie() 679 val32 = SET_CLR_WORD(val32, DBI_WEN_DW, B_AX_DBI_WREN); in dbi_w32_pcie() 717 val32 = SET_CLR_WORD(val32, r_addr, B_AX_DBI_ADDR); in dbi_r8_pcie() 759 val32 = SET_CLR_WORD(val32, w_addr, B_AX_DBI_ADDR); in dbi_w8_pcie() 760 val32 = SET_CLR_WORD(val32, DBI_WEN_B << addr_2lsb, B_AX_DBI_WREN); in dbi_w8_pcie() 800 val16 = SET_CLR_WORD(val16, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR); in mdio_r16_pcie() 802 val16 = SET_CLR_WORD(val16, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR); in mdio_r16_pcie() 804 val16 = SET_CLR_WORD(val16, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR); in mdio_r16_pcie() 806 val16 = SET_CLR_WORD(val16, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR); in mdio_r16_pcie() [all …]
H A D	dle.c	2516 val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_64, in dle_mix_cfg() 2520 val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_128, in dle_mix_cfg() 2528 val32 = SET_CLR_WORD(val32, bound, B_AX_WDE_START_BOUND); in dle_mix_cfg() 2529 val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num, in dle_mix_cfg() 2544 val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_128, in dle_mix_cfg() 2548 val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_256, in dle_mix_cfg() 2553 val32 = SET_CLR_WORD(val32, bound, B_AX_PLE_START_BOUND); in dle_mix_cfg() 2554 val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num, in dle_mix_cfg() 2897 val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q6_MAX_SIZE); in _patch_redu_rx_qta() 2910 val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q7_MAX_SIZE); in _patch_redu_rx_qta() [all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/
H A D	rx_forwarding.c	133 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_CSA); in af_fwd_cfg() 136 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_REQ); in af_fwd_cfg() 139 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDTS_RES); in af_fwd_cfg() 142 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELTS); in af_fwd_cfg() 145 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_REQ); in af_fwd_cfg() 148 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_ADDBA_RES); in af_fwd_cfg() 151 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_DELBA); in af_fwd_cfg() 154 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_NCW); in af_fwd_cfg() 157 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_GID_MGNT); in af_fwd_cfg() 160 val32 = SET_CLR_WORD(val32, fwd_tg, B_AX_FWD_OP_MODE); in af_fwd_cfg() [all …]
H A D	dbgport_hw.c	58 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 73 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 85 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 101 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 130 val32 = SET_CLR_WORD(val32, intn_val, B_AX_DBG_SEL); in dp_intn_idx_set() 147 val32 = SET_CLR_WORD(val32, intn_idx, B_AX_DBG_SEL); in dp_intn_idx_set() 249 val32 = SET_CLR_WORD(val32, intn_val, B_PL_AXIDMA_DBG_SEL); in dp_intn_idx_set() 357 val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG0_SEL); in dp_intn_idx_set() 358 val16 = SET_CLR_WORD(val16, intn_val, B_AX_WDE_DBG1_SEL); in dp_intn_idx_set() 451 val16 = SET_CLR_WORD(val16, intn_val, B_AX_PLE_DBG0_SEL); in dp_intn_idx_set() [all …]
H A D	dbgpkg.c	1975 val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC, in dbg_port_sel() 1980 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); in dbg_port_sel() 1981 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); in dbg_port_sel() 1985 val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); in dbg_port_sel() 1992 val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_TMAC, in dbg_port_sel() 1997 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); in dbg_port_sel() 1998 val32 = SET_CLR_WORD(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); in dbg_port_sel() 2002 val32 = SET_CLR_WORD(val32, MAC_DBG_SEL, B_AX_SEL_0XC0); in dbg_port_sel() 2009 val32 = SET_CLR_WORD(val32, TRXPTRL_DBG_SEL_RMAC, in dbg_port_sel() 2014 val32 = SET_CLR_WORD(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); in dbg_port_sel() [all …]
H A D	mport.c	552 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 556 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 560 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 564 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 568 w_val32 = SET_CLR_WORD(val32, set_val, in _port_cfg() 933 w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM); in _set_max_mbid_num() 940 w_val32 = SET_CLR_WORD(val32, subspc, B_AX_SUB_BCN_SPACE_P0); in _set_max_mbid_num() 942 w_val32 = SET_CLR_WORD(val32, 0, B_AX_SUB_BCN_SPACE_P0); in _set_max_mbid_num() 956 w_val32 = SET_CLR_WORD(val32, mbid_num, B_AX_P0MB_NUM); in port0_mbid_set() 989 w_val32 = SET_CLR_WORD(val32, subspc_u32, B_AX_SUB_BCN_SPACE_P0); in port0_subspc_set() [all …]
H A D	trxcfg.c	935 val32 = SET_CLR_WORD(val32, SIFS_MACTXEN_T1, B_AX_SIFS_MACTXEN_T1); in scheduler_init() 954 val32 = SET_CLR_WORD(val32, SCH_PREBKF_16US, B_AX_PREBKF_TIME); in scheduler_init() 960 val32 = SET_CLR_WORD(val32, 0x6a, B_AX_R_SIFS_AGGR_TIME); in scheduler_init() 966 val32 = SET_CLR_WORD(val32, SCH_PREBKF_24US, B_AX_PREBKF_TIME); in scheduler_init() 1050 val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_FPGA, in tmac_init() 1053 val32 = SET_CLR_WORD(val32, LBK_PLCP_DLY_DEF, in tmac_init() 1073 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_CCK, in trxptcl_init() 1076 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52A, in trxptcl_init() 1079 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52B, in trxptcl_init() 1082 val32 = SET_CLR_WORD(val32, WMAC_SPEC_SIFS_OFDM_52C, in trxptcl_init() [all …]
H A D	spatial_reuse.c	`43 val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_min, in mac_sr_update() 45 val32 = SET_CLR_WORD(val32, sr_info->non_srg_obss_pd_max, in mac_sr_update() 47 val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_min, in mac_sr_update() 49 val32 = SET_CLR_WORD(val32, sr_info->srg_obss_pd_max, in mac_sr_update()`
H A D	cpuio.c	55 val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_WD_BUF_REQ_LEN); in mac_dle_buf_req_wd() 91 val32 = SET_CLR_WORD(val32, buf_req_p->len, B_AX_PL_BUF_REQ_LEN); in mac_dle_buf_req_pl() 130 val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->start_pktid, in mac_set_cpuio_wd() 132 val_op2 = SET_CLR_WORD(val_op2, ctrl_para_p->end_pktid, in mac_set_cpuio_wd() 137 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_pid, in mac_set_cpuio_wd() 139 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->src_qid, in mac_set_cpuio_wd() 141 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_pid, in mac_set_cpuio_wd() 143 val_op1 = SET_CLR_WORD(val_op1, ctrl_para_p->dst_qid, in mac_set_cpuio_wd() 148 val_op0 = SET_CLR_WORD(val_op0, cmd_type, in mac_set_cpuio_wd() 150 val_op0 = SET_CLR_WORD(val_op0, ctrl_para_p->macid, in mac_set_cpuio_wd() [all …]
H A D	coex.c	119 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3, in mac_coex_init() 143 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE); in mac_coex_init() 223 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_0_3, in mac_coex_init() 231 val = SET_CLR_WORD(val, MAC_AX_RTK_RATE, in mac_coex_init() 237 val = SET_CLR_WORD(val, MAC_AX_BT_MODE_2, B_AX_BTMODE); in mac_coex_init() 241 val16 = SET_CLR_WORD(val16, MAC_AX_CSR_PRI_TO, in mac_coex_init() 243 val16 = SET_CLR_WORD(val16, MAC_AX_CSR_TRX_TO, in mac_coex_init() 245 val16 = SET_CLR_WORD(val16, MAC_AX_CSR_DELAY, in mac_coex_init()
H A D	hwamsdu.c	`171 val = SET_CLR_WORD(val, low_th, B_AX_BIT_CUT_AMSDU_CHKLEN_L_TH); in mac_enable_cut_hwamsdu() 172 val = (SET_CLR_WORD(val, high_th, B_AX_BIT_CUT_AMSDU_CHKLEN_H_TH) \| in mac_enable_cut_hwamsdu() 182 val = (SET_CLR_WORD(val, aligned, B_AX_EXTRA_SHIFT)); in mac_enable_cut_hwamsdu() 210 val = (SET_CLR_WORD(val, max_num, B_AX_MAX_AMSDU_NUM) \| in mac_enable_hwmasdu()`
H A D	dle.c	2516 val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_64, in dle_mix_cfg() 2520 val32 = SET_CLR_WORD(val32, S_AX_WDE_PAGE_SEL_128, in dle_mix_cfg() 2528 val32 = SET_CLR_WORD(val32, bound, B_AX_WDE_START_BOUND); in dle_mix_cfg() 2529 val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num, in dle_mix_cfg() 2544 val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_128, in dle_mix_cfg() 2548 val32 = SET_CLR_WORD(val32, S_AX_PLE_PAGE_SEL_256, in dle_mix_cfg() 2553 val32 = SET_CLR_WORD(val32, bound, B_AX_PLE_START_BOUND); in dle_mix_cfg() 2554 val32 = SET_CLR_WORD(val32, size_cfg->lnk_pge_num, in dle_mix_cfg() 2897 val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q6_MAX_SIZE); in _patch_redu_rx_qta() 2910 val32 = SET_CLR_WORD(val32, new_qta, B_AX_PLE_Q7_MAX_SIZE); in _patch_redu_rx_qta() [all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/mac_8852b/
H A D	_usb_8852b.c	236 val8 = SET_CLR_WORD(val8, EP5, B_AX_EP_IDX); in usb_init_8852b() 240 val8 = SET_CLR_WORD(val8, EP6, B_AX_EP_IDX); in usb_init_8852b() 244 val8 = SET_CLR_WORD(val8, EP7, B_AX_EP_IDX); in usb_init_8852b() 248 val8 = SET_CLR_WORD(val8, EP9, B_AX_EP_IDX); in usb_init_8852b() 252 val8 = SET_CLR_WORD(val8, EP10, B_AX_EP_IDX); in usb_init_8852b() 256 val8 = SET_CLR_WORD(val8, EP11, B_AX_EP_IDX); in usb_init_8852b() 260 val8 = SET_CLR_WORD(val8, EP12, B_AX_EP_IDX); in usb_init_8852b() 276 value32 = SET_CLR_WORD(value32, offset - phyoffset, in read_usb2phy_para_8852b() 298 value32 = SET_CLR_WORD(value32, val, B_AX_USB_SIE_INTF_WD); in write_usb2phy_para_8852b() 299 value32 = SET_CLR_WORD(value32, offset, B_AX_USB_SIE_INTF_ADDR); in write_usb2phy_para_8852b() [all …]
H A D	pwr_seq_func_8852b.c	84 val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); in mac_pwr_on_sdio_8852b() 85 val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); in mac_pwr_on_sdio_8852b() 308 val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1); in mac_pwr_on_sdio_8852b() 309 val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L); in mac_pwr_on_sdio_8852b() 365 val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); in mac_pwr_on_usb_8852b() 366 val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); in mac_pwr_on_usb_8852b() 589 val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1); in mac_pwr_on_usb_8852b() 590 val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L); in mac_pwr_on_usb_8852b() 647 val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); in mac_pwr_on_pcie_8852b() 648 val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); in mac_pwr_on_pcie_8852b() [all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/mac_8852b/
H A D	_usb_8852b.c	236 val8 = SET_CLR_WORD(val8, EP5, B_AX_EP_IDX); in usb_init_8852b() 240 val8 = SET_CLR_WORD(val8, EP6, B_AX_EP_IDX); in usb_init_8852b() 244 val8 = SET_CLR_WORD(val8, EP7, B_AX_EP_IDX); in usb_init_8852b() 248 val8 = SET_CLR_WORD(val8, EP9, B_AX_EP_IDX); in usb_init_8852b() 252 val8 = SET_CLR_WORD(val8, EP10, B_AX_EP_IDX); in usb_init_8852b() 256 val8 = SET_CLR_WORD(val8, EP11, B_AX_EP_IDX); in usb_init_8852b() 260 val8 = SET_CLR_WORD(val8, EP12, B_AX_EP_IDX); in usb_init_8852b() 276 value32 = SET_CLR_WORD(value32, offset - phyoffset, in read_usb2phy_para_8852b() 298 value32 = SET_CLR_WORD(value32, val, B_AX_USB_SIE_INTF_WD); in write_usb2phy_para_8852b() 299 value32 = SET_CLR_WORD(value32, offset, B_AX_USB_SIE_INTF_ADDR); in write_usb2phy_para_8852b() [all …]
H A D	pwr_seq_func_8852b.c	84 val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); in mac_pwr_on_sdio_8852b() 85 val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); in mac_pwr_on_sdio_8852b() 308 val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1); in mac_pwr_on_sdio_8852b() 309 val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L); in mac_pwr_on_sdio_8852b() 365 val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); in mac_pwr_on_usb_8852b() 366 val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); in mac_pwr_on_usb_8852b() 589 val32 = SET_CLR_WORD(val32, 0x9, B_AX_VOL_L1); in mac_pwr_on_usb_8852b() 590 val32 = SET_CLR_WORD(val32, 0xA, B_AX_VREFPFM_L); in mac_pwr_on_usb_8852b() 647 val32 = SET_CLR_WORD(val32, 0x1, B_AX_C1_L1); in mac_pwr_on_pcie_8852b() 648 val32 = SET_CLR_WORD(val32, 0x3, B_AX_C3_L1); in mac_pwr_on_pcie_8852b() [all …]

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