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Searched refs:RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c5488 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v8_0_get_clockgating_state()
5783 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v8_0_update_coarse_grain_clock_gating()
5791 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v8_0_update_coarse_grain_clock_gating()
5832 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v8_0_update_coarse_grain_clock_gating()
H A Dgfx_v6_0.c2584 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v6_0_enable_cgcg()
2593 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v6_0_enable_cgcg()
H A Dgfx_v7_0.c3604 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v7_0_enable_cgcg()
3616 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v7_0_enable_cgcg()
H A Dgfx_v9_0.c4982 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v9_0_update_coarse_grain_clock_gating()
4995 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v9_0_update_coarse_grain_clock_gating()
5181 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v9_0_get_clockgating_state()
H A Dgfx_v10_0.c7474 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v10_0_update_coarse_grain_clock_gating()
7487 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v10_0_update_coarse_grain_clock_gating()
7670 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v10_0_get_clockgating_state()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7066 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L macro
H A Dgfx_7_2_sh_mask.h7889 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 macro
H A Dgfx_8_1_sh_mask.h9357 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 macro
H A Dgfx_8_0_sh_mask.h8807 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23124 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h24476 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_9_1_sh_mask.h24415 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_10_1_0_sh_mask.h33462 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_10_3_0_sh_mask.h32504 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro