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Searched refs:RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c4976 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v9_0_update_coarse_grain_clock_gating()
4979 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v9_0_update_coarse_grain_clock_gating()
4995 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v9_0_update_coarse_grain_clock_gating()
5177 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) in gfx_v9_0_get_clockgating_state()
H A Dgfx_v6_0.c2584 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v6_0_enable_cgcg()
2593 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v6_0_enable_cgcg()
H A Dgfx_v7_0.c3604 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v7_0_enable_cgcg()
3616 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v7_0_enable_cgcg()
H A Dgfx_v8_0.c5484 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) in gfx_v8_0_get_clockgating_state()
5779 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v8_0_update_coarse_grain_clock_gating()
5831 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | in gfx_v8_0_update_coarse_grain_clock_gating()
H A Dgfx_v10_0.c7471 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v10_0_update_coarse_grain_clock_gating()
7487 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v10_0_update_coarse_grain_clock_gating()
7666 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) in gfx_v10_0_get_clockgating_state()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7060 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h7887 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h9355 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h8805 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23123 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h24475 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK … macro
H A Dgc_9_1_sh_mask.h24414 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK … macro
H A Dgc_10_1_0_sh_mask.h33461 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK … macro
H A Dgc_10_3_0_sh_mask.h32503 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK … macro