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Searched refs:REG_PHY_CS_OFFS (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c557 reg |= ((0x4 * cs + mode) << REG_PHY_CS_OFFS); in ddr3_write_pup_reg()
581 reg |= ((0x4 * cs + mode + 1) << REG_PHY_CS_OFFS); in ddr3_write_pup_reg()
603 ((0x4 * cs + mode) << REG_PHY_CS_OFFS); in ddr3_read_pup_reg()
825 reg = (val >> REG_PHY_CS_OFFS) & 0x3F; /*read the phy address */ in ddr3_read_training_results()
H A Dddr3_axp.h310 #define REG_PHY_CS_OFFS 16 macro
H A Dddr3_write_leveling.c1356 reg |= (reg_addr << REG_PHY_CS_OFFS); in ddr3_write_ctrl_pup_reg()
H A Dddr3_pbs.c1517 reg |= ((0x4 * cs + PUP_WL_MODE) << REG_PHY_CS_OFFS); in ddr3_pbs_write_pup_dqs_reg()
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_hws_hw_training_def.h284 #define REG_PHY_CS_OFFS 16 macro