Searched refs:REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG (Results 1 – 2 of 2) sorted by relevance
211 pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); in dsi_pll_28nm_clk_set_rate()
1145 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 macro