Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG7 (Results 1 – 2 of 2) sorted by relevance
233 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); in dsi_pll_28nm_clk_set_rate()
1246 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 macro